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By SOI_Sentinel
Most of you know about the Bitscope. The original design was an open source digital storage oscilloscope and 8 bit logic analyzer. Still does that, but they've thrown on a few other things (waveform generator, etc).

The original specs were:
100MHz bandwidth
25MSPS 8 bit ADC
32K sample depth for the ADC
32K sample depth for the Logic analyzer
Serial connection
PIC rear end virtual machine
CPLD logic for capture operation

Now, I've been looking around for something similar, although I've REALLY been itching to just build my own digital storage O-scope :) This is a group thought experiment I'd like some other people's input on. It may never get built, but not everyone's worked on the same stuff.

So, here's some thoughts on what I'm thinking of doing. The main objective is to get as high a speed as possible while keeping the design PIC based and keeping away from CPLD's and other hardware that requires special design software and programmers.

Core Design
-PIC18F4550 for control and transfer. Built in USB is good, planning to use Microchip's serial port profile.
-TI SN74V293 64K/18 bit or 128K/9 bit sync FIFO. I may chain a few together to deepen the buffer. They're a WHOLE lot cheaper than Cypress's 129K/9 bit offering. I'm considering using the on the fly reconfigurability to allow a user to switch the logic analyser portion.
-Socketed can oscillator for memory/ADC time clock. May also need a counter in there for frequency division.
-All 18 bits are to be buffered for logic analyzer work.
-May need a S-R flipflop for logic-triggered capture enable.

Now, from here, we drive either plug in or cable connected modules...

Analog Portion
Module 1: High Speed
-Still deciding on the ADC. May run from 8 to 16 bits in width. Probably aim for 40MSPS if it's 8 bit. This will probably provide your standard BNC connection for probes. Original idea combined this module, one FIFO and a PIC into a "USB O scope pen"

Module 2: Adaptable ADC
Lower speed module running an Anadigm FPAA front end. These are easily configured via SPI, and need no special software (but they do have filter design software available). Multiple units and a serial output ADC may be used for parallel ADC work.

Possible issues:
-May need a 4 layer board for isolation issues.
-Depending on options, power may be too much for a USB bus powered solution
-Cannot exploit the full speed USB bus without custom drivers

This is a lot better than my original ideas at least. I was going to use an FPGA to dump data from at least one 200MSPS 8 bit ADC into DDR SDRAM on a DIMM. WAAAAAY overboard for a first foray into high speed mixed signal work.

Thoughts, comments, additions, subtractions? Although links to other Oscope projects are always welcome(especially analog end schematics), part of this little exercise is to understand the issues in building high speed mixed signal and oscilloscopes.
By pittuck
Huummm, Microchip Serial Profile Eh? Will limit output speed, if you want a live on screen output.

Not checked but i think the MSCOMM control is limited to 256 000 baud or 32,000 kilo bytes per second. Making a total of (At 100% efficiency, or 100% of the data as actual 16bit readings). 16,000 kilo bytes per second or 16MBps

SO with one probe the max number of readings per second will be 16MSPS, which is OK, but does mean there is not a 'lot' of improvement for extra inputs and/or control data.

So i suppose using a USB->RS232 like Microchip drivers can do would mean a speed of about 15MSPS allowing enough baud to other input information.

Perhaps using a USB1.1 or USB2 (I would shy away from 2 ATM, its ok but some people still use 1.1) would be better. I forget the speeds but it should be faster then serial....

A quick google says that USB1 is only 12MBps, humm, lol. So serial can be faster, BUT u will have to keep cable lengths 'short' or well shielded to stop interfearance. And thats using the official MS serial port control, which is not included in the latest versions of (and only useable if you have had an old version installed at some point)

So, whats your PC side going to be? I think that will be the limiting factor in the experiment ;).
By SOI_Sentinel
Ok, I think you either need sleep or have been drinking the same stuff tonight that a friend of mine has... :-D

Microchip's USB PICs his 12Mbps max (USB2.0 Full speed). The serial profile IIRC does around 1Mbps. Ethernet would be interesting if I could pull off the full 10Mbps. Mind you, this all falls into the range of at most 1.5MS/S live feed from an 8 bit ADC via a 100% utilized USB connection. I'd love to implement bulk transfer and just dump that data through the system at full speed, but that's not critical right now. So, at best, cranking down the sampling rate (either via gating the oscillator or via digital decimation) would allow a decent live feed.

So, live feed is really NOT much of an option for the hopeful sample speeds (10-40MS/s). The USB is more for transfers than anything. Never expected it to be. I could buffer 128K samples (One chip, 8 bit ADC) of the scope, which is pretty decent. Then I see two options: either upload to a PC, or transfer to an SD card (interesting idea, but I have no real reason for that option). Current plan is to dump data into the FIFO at sample rate and remove it from the other end via the PIC, limited by transfer rate. This would give me, basically, 65-128Ksamples of data in a very short time period. I'd definitely need that trigger line. Another option I'm considering is using the "reread data" command commonly available to lock out the ADC while the system digitally decimates and transmits a shortened version of the data to the PC (optional), then transmits the full frame, then release to capture another full buffer.

It does make me appreciate the CPLD capture engine from the Bitscope, although they're more limited in capture rate. I have this feeling I might end up back at the FPGA super Bitscope at this rate :) 200MS/S * 8 bit = 200MB/s. Kinda explains why those pro scopes are so expensive. The electronics are expensive, but the RAM is even more so.

Still thinking... and poking through TI and National datasheets


Yeah, looks like I'm limited to 640Kbps from what I've found while skimming the site. I'll have to look over their code and see if I can overdrive it via running the SPP port full out for bulk data transferal.

Power is also going to be problematic due to 5V/3.3V splits and need for a clean analog power supply. I'd like to make it bus powered, but having it separated from the comp would be useful, too. Was joking with a friend about running a single ADC "pen" off of two "C" cells and using a bluetooth serial link instead. :)
By pittuck
Lol, it was 7:30AM local time on a sat morining ;) lol.
By doragasu
Just it case you don't know, USB 2.0 specification supports 3 speeds:

- Low Speed = 1,5 Mbps
- Full Speed = 12 Mbps
- High Speed = 480 Mbps

Low Speed and Full Speed are also supported in USB 1.1 devices. High Speed is only available for 2.0 devices. So maybe you should try to find a USB chip supporting USB 2.0 High Speed Isochronous transfers to get rid of any bandwith problems that could arise.
By Tre
Check out the CCS sample code, it contains a very primitive USB Scope. Supports Full Speed USB 2.0.. may or may not be helpful.
By DynamoBen
I'm not sure if this is useful but Nuts and Volts magazine is doing a two parts series for the construction of a multi channel logic analyzer. Article is called "THE ULTIMATE UTILITY METER."
By asm2750
I would like to get in on this, Ive been thinking of just trying to make an Oscope instead of buying one hehe.
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