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[shirley]

i'm using a c8051f530 and it's SPI interface talk to nRF24L01,the thing i need program quite simple infact.just transmite the data every 0.1 sec at transmiter side and the receiver will read out the data once the data is received.not so care about the data lost.
i already write the code for both side.but find it doesn't works.now i even dont know which part get the problems.or both side.can someone help me check my code?cause i really outside this things.thx alot
really hurry for this,help me please,and really thx alotttttttt

following is the code i write:
----------------------------------TX----------------------------------------------------
#include<c8051f520.h> // SFR declarations

sbit CE=P0^4;
sbit CSN=P0^3;

int n,x;
int status;

void MAIN()
{
PCA0MD=0x00; // Disable watchdog timer
OSCICN=0xD7; // Sysclk is set to be 24.5MHz

P0MDIN=0xFF; // Select port0 for digital input
P0MDOUT=0x1F; // Select pin0-4 of port0 is PUSH PULL output
XBR0=0x02; // SPI AND UART ENABLE AT PORT PIN
XBR1=0x40; // CROSSBAR AND T0 ENABLE

SPI0CFG=0x40; // MASTER MODE
SPI0CN=0x03; // 3 WIRE SLAVE AND 3 WIRE MASTER MODE,SPI ENABLE
SPI0CKR=0x03; // Transfer CLK is 250 kHz

n=10;

CSN=1;
CE=0; // STAND BY

CSN=0;
SPI0DAT=0x20; // WRITE CONFIG REGISTER
while(SPIF==0)
{
}
SPIF=0;
SPI0DAT=0x0A; // 1BYTE CRC,POWER UP,PTX ENABLE
while(SPIF==0)
{
}
SPIF=0;
CSN=1;

CSN=0;
SPI0DAT=0x24; // WRITE SETUP REGISTER
while(SPIF==0)
{
}
SPIF=0;
SPI0DAT=0x05; // RETRANSMIT 5 TIMES WITH 250US DELAY
while(SPIF==0)
{
}
SPIF=0;
CSN=1;

CSN=0;
SPI0DAT=0x27; // WRITE STATUS REGISTER
while(SPIF==0)
{
}
SPIF=0;
SPI0DAT=0x7E; // CLEAR FLAG,TX&RX FIFO EMPTY
while(SPIF==0)
{
}
SPIF=0;
CSN=1;

CSN = 0;
SPI0DAT = 0x31; // Access RX_PW_P0
while (SPIF == 0)
{
}
SPIF = 0;
SPI0DAT = 0x01; // 1 byte RX payload
while (SPIF == 0)
{
}
SPIF = 0;
CSN = 1;

CSN=0;
SPI0DAT=0x37; // WRITE FIFO_STATUS REGISTER
while(SPIF==0)
{
}
SPIF=0;
SPI0DAT=0x31; // CLEAR ALL FLAG
while(SPIF==0)
{
}
SPIF=0;
CSN=1;

CSN=0;
SPI0DAT=0xE1; // FLUSH_TX
while(SPIF==0)
{
}
SPIF=0;
CSN=1;

CSN=0;
SPI0DAT=0xE2; // FLUSH_RX
while(SPIF==0)
{
}
SPIF=0;
CSN=1;

while(1)
{
CSN=0;
SPI0DAT = 0xA0; // Write payload
while (SPIF == 0)
{
}
SPIF = 0;
SPI0DAT = n; // 1st data byte
while (SPIF == 0)
{
}
SPIF = 0;
CSN = 1;

CE = 1; // Start transmisson
n++;
CE = 0; // End transmission

CSN = 0;
SPI0DAT = 0x07; // Access STATUS register
while (SPIF == 0)
{
}
SPIF = 0;
SPI0DAT = 0x88;
while (SPIF == 0)
{
}
SPIF = 0;
status = SPI0DAT;
status &= 0x20;
CSN = 1;

if(status==0x20)
{
CSN=0;
SPI0DAT=0x37; // WRITE FIFO_STATUS REGISTER
while(SPIF==0)
{
}
SPIF=0;
SPI0DAT=0x31; // CLEAR ALL FLAG
while(SPIF==0)
{
}
SPIF=0;
CSN=1;

CSN=0;
SPI0DAT=0xE1; // FLUSH_TX
while(SPIF==0)
{
}
SPIF=0;
CSN=1;

CSN=0;
SPI0DAT=0xE2; // FLUSH_RX
while(SPIF==0)
{
}
SPIF=0;
CSN=1;
}
for (x = 3000; x > 0; x--) // For 0.1 second
{
}




}

}
-----------------------------RX------------------------------------------------------
#include<c8051f520.h> // SFR declarations

sbit CE=P0^4;
sbit CSN=P0^3;

int Q;
int Status;


void MAIN()
{
PCA0MD=0x00; // Disable watchdog timer
OSCICN=0xD7; // Sysclk is set to be 24.5MHz

P0MDIN=0xFF; // Select port0 for digital input
P0MDOUT=0x1F; // Select pin0-4 of port0 is PUSH PULL output
XBR0=0x02; // SPI AND UART ENABLE AT PORT PIN
XBR1=0x40; // CROSSBAR AND T0 ENABLE

SPI0CFG=0x40; // MASTER MODE
SPI0CN=0x03; // 3 WIRE SLAVE AND 3 WIRE MASTER MODE,SPI ENABLE
SPI0CKR=0x03; // Transfer CLK is 250 kHz

CSN=1;
CE=0; // STAND BY

CSN=0;
SPI0DAT=0x20; // WRITE CONFIG REGISTER
while(SPIF==0)
{
}
SPIF=0;
SPI0DAT=0x0B; // 1BYTE CRC,POWER UP,PRX ENABLE
while(SPIF==0)
{
}
SPIF=0;
CSN=1;

CSN=0;
SPI0DAT=0x24; // WRITE SETUP REGISTER
while(SPIF==0)
{
}
SPIF=0;
SPI0DAT=0x05; // RETRANSMIT 5 TIMES WITH 250US DELAY
while(SPIF==0)
{
}
SPIF=0;
CSN=1;


CSN=0;
SPI0DAT=0x27; // WRITE STATUS REGISTER
while(SPIF==0)
{
}
SPIF=0;
SPI0DAT=0x7E; // CLEAR all FLAG
while(SPIF==0)
{
}
SPIF=0;
CSN=1;

CSN = 0;
SPI0DAT = 0x31; // Access RX_PW_P0
while (SPIF == 0)
{
}
SPIF = 0;
SPI0DAT = 0x01; // 1 byte RX payload
while (SPIF == 0)
{
}
SPIF = 0;
CSN = 1;


CSN=0;
SPI0DAT=0xE1; // FLUSH_TX
while(SPIF==0)
{
}
SPIF=0;
CSN=1;

CSN=0;
SPI0DAT=0xE2; // FLUSH_RX
while(SPIF==0)
{
}
SPIF=0;
CSN=1;
CE=1;

while(1)
{
CSN = 0;
SPI0DAT = 0x07; // Access STATUS register
while (SPIF == 0)
{
}
SPIF = 0;
SPI0DAT = 0x88;
while (SPIF == 0)
{
}
SPIF = 0;
Status = SPI0DAT;
Status &= 0x40;
CSN = 1;

if(Status==0x40)
{
CE=0;

CSN=0;
SPI0DAT = 0x61; // READ payload
while (SPIF == 0)
{
}
SPIF = 0;
Q=SPI0DAT; // READ ONE data byte
CSN = 1;

CSN=0;
SPI0DAT=0xE2; // FLUSH_RX
while(SPIF==0)
{
}
SPIF=0;
CSN=1;

CE=1;
}

CSN = 0;
SPI0DAT = 0x27; // Access STATUS register
while (SPIF == 0)
{
}
SPIF = 0;
SPI0DAT = 0x7E; // Clear all flag
while (SPIF == 0)
{
}
SPIF = 0;
CSN = 1;

CSN = 0;
SPI0DAT = 0x20; // Access CONFIG register
while (SPIF == 0)
{
}
SPIF = 0;
SPI0DAT = 0x0B; // Powered up, RX, 1Bytes CRC
while (SPIF == 0)
{
}
SPIF = 0;
CSN = 1;

CSN = 0;
SPI0DAT = 0xE1; // Flush TX FIFO
while (SPIF == 0)
{
}
SPIF = 0;
CSN = 1;

CE = 1;

}



}

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