The original specs were:
25MSPS 8 bit ADC
32K sample depth for the ADC
32K sample depth for the Logic analyzer
PIC rear end virtual machine
CPLD logic for capture operation
Now, I've been looking around for something similar, although I've REALLY been itching to just build my own digital storage O-scope This is a group thought experiment I'd like some other people's input on. It may never get built, but not everyone's worked on the same stuff.
So, here's some thoughts on what I'm thinking of doing. The main objective is to get as high a speed as possible while keeping the design PIC based and keeping away from CPLD's and other hardware that requires special design software and programmers.
-PIC18F4550 for control and transfer. Built in USB is good, planning to use Microchip's serial port profile.
-TI SN74V293 64K/18 bit or 128K/9 bit sync FIFO. I may chain a few together to deepen the buffer. They're a WHOLE lot cheaper than Cypress's 129K/9 bit offering. I'm considering using the on the fly reconfigurability to allow a user to switch the logic analyser portion.
-Socketed can oscillator for memory/ADC time clock. May also need a counter in there for frequency division.
-All 18 bits are to be buffered for logic analyzer work.
-May need a S-R flipflop for logic-triggered capture enable.
Now, from here, we drive either plug in or cable connected modules...
Module 1: High Speed
-Still deciding on the ADC. May run from 8 to 16 bits in width. Probably aim for 40MSPS if it's 8 bit. This will probably provide your standard BNC connection for probes. Original idea combined this module, one FIFO and a PIC into a "USB O scope pen"
Module 2: Adaptable ADC
Lower speed module running an Anadigm FPAA front end. These are easily configured via SPI, and need no special software (but they do have filter design software available). Multiple units and a serial output ADC may be used for parallel ADC work.
-May need a 4 layer board for isolation issues.
-Depending on options, power may be too much for a USB bus powered solution
-Cannot exploit the full speed USB bus without custom drivers
This is a lot better than my original ideas at least. I was going to use an FPGA to dump data from at least one 200MSPS 8 bit ADC into DDR SDRAM on a DIMM. WAAAAAY overboard for a first foray into high speed mixed signal work.
Thoughts, comments, additions, subtractions? Although links to other Oscope projects are always welcome(especially analog end schematics), part of this little exercise is to understand the issues in building high speed mixed signal and oscilloscopes.