- Fri Oct 04, 2019 8:03 am
The "run mode" current numbers are slippery. From the data sheet pg 776, the "6 uA per MHz" spec only applies when "Executing while(1) from internal Flash Memory, cache enabled, HFRC=48MHz, all peripherals disabled, buck converters enabled, 8K SRAM, Flash1 OFF". So basically, minimal system SRAM is powered up, half the flash turned off, no peripherals turned on. The processor will be hitting in the cache for every instruction of its while (1) loop so the flash will never be getting accessed. It's an unlikely scenario for any real program, but serves to place a lower bound on the power you could expect to be consumed by a running processor: 288 uA (48 MHz * 6 uA/MHz). No running program you every write will take less power than that, at least at 48 MHz.
If you read the very next item in the data sheet power section describing power state ISS2, it says that the current draw is 68 uA when "WFI instruction with SLEEP=1, clocks gated, OSC's ON, buck converters enabled, all I/O power domains powered OFF, Flash1 OFF, 8kB SRAM". That is saying that with the CPU shut down doing nothing at all (basically in a hot standby) the current draw is 68 uA. Therefore, it seems unlikely that any power mode that involves the CPU actually executing instructions could draw less power than that: how could a processor doing something take less power than the exact same processor doing nothing? In my mind, the implication is that we don't get to assume that a 48 MHz clock divided down to produce a 3 MHz processor clock means that the processor will be running at 3 MHz * 6 uA/MHz, or 18 uA. I think I have a bit of proof for that. My experiments to get the processor into deep sleep mode showed that turning on any part of the chip that depended on the 48 MHz oscillator caused the power to increase by about 60 uA. My assumption was that the HFRC itself takes 60 uA. A subsequent assumption would be that the HFRC would still take 60 uA no matter what you divided it down by. If all that is true, then it makes me wonder if the "per MHz" in the data sheet always refers to 48 MHz because the HFRC only ever runs at 48 MHz. That clock can be divided, but the basic osc freq is always 48 MHz. At this point, this is mostly conjecture so I think some experimentation is in order...