Thanks for the feedback n1ist,
I made a revision and also have some more questions if you're willing to help. I will try to answer your questions/feedback in sequential order
1 - I changed the most of the power connections to pours rather than traces as you suggested. I'll post the most recent revision below:
Board Revision.PNG
2 - I rearranged components and followed data sheets such that the gate lengths were as short as possible. I believe I tried to use small pours.
3 - Thanks for the low s and GND catch, I updated the schematic and fixed that connection.
4 - I believe the reason that I had no ground pin on JP3 is because they are considered to be coming from the same controller source. I (arbitrarily) chose to use 2 pin screw terminals, but both will likely be sourced from a controller. This board was really only a simple prototyping/testing of the GaN FETs and TI driver chip - for internal use. Do you think it would be worthwhile to add the ground pin anyway, just in case the power might be an external source?
5 - I decided against mounting holes because I don't necessarily need to mount it anywhere and I think it should be okay.
6 - I forgot to add a board name (I'll have to go back and add that in) but I added some info. to the bottom silk. I assume it is convention to add to the top instead of the bottom? Or possibly both?
7 - I added more vias between top and bottom ground, but do you think my method of connecting the low side source to ground will be effective or would you go about it differently?
I also have a few DRC errors and questions that I wanted to ask about and I added pictures below:
Value on Silkscreen.PNG
With respect to this picture, will the value show up on the silkscreen as it appears that it will? That being asked, do names of components show up on silkscreen as well?
The DRC errors were a "width" error:
Width Error.PNG
I havent gotten this before and I am not exactly sure what it means. Any thoughts?
Thanks for all of the help and feel free to question the assertions I made earlier
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