SparkFun Forums

[gjsmo]

I've never done PCB design before, so forgive me if this is a piece of crap... but can someone look at this design:
https://dl.dropboxusercontent.com/u/707 ... ulator.brd

It's a USB power supply, using the TS30013 DC/DC chip here: http://www.mouser.com/ProductDetail/Tri ... DP4v3b4%3d
Schematic here: https://dl.dropboxusercontent.com/u/707 ... ulator.sch
I'm pretty certain it will work, I've done a few of these before, but it's somewhat hard to test an SMT design, at least for someone who's used to 10x40 breadboarding, and then moving that to an equivalent protoboard. I'm not really looking for schematic help, I can figure that out for myself.

I'm going to be ordering it from OSH Park, but it doesn't conform to their DRC - specifically, there's some clearances which I can't change, and some overlaps in the copper layers which I don't know how to eliminate.
> The clearances issues are all in the QFN16 regulator chip, and the footprint is defined by the TS30013 datasheet. I can't really fix this - or can I?
> The overlaps are for manually placed vias - 4 for a power ground connection, and 1 thermal via underneath the regulator (necessary as per the datasheet). I realize that there's a via and a trace in the same spot, but I don't know what to do about it.

What do I do about these? How's my PCB design? Any help is appreciated.

[dlotton]

> The clearances issues are all in the QFN16 regulator chip, and the footprint is defined by the TS30013 datasheet. I can't really fix this - or can I?

I didn't inspect your QFN part closely, so I'm not sure how much space you need to make the DRC happy. If you just need a few mils, you could make a copy of that library footprint and make the SMT pads slightly narrower. You might want to make the pads extend slightly further from under the part, too. This helps if you need to touch-up the solder with an iron.

> The overlaps are for manually placed vias - 4 for a power ground connection, and 1 thermal via underneath the regulator (necessary as per the datasheet). I realize that there's a via and a trace in the same spot, but I don't know what to do about it.

Will post back in a bit...

[dlotton]

Overall, the flow and component placement looks pretty good. You've got some massive traces on the the USB data lines, which restricts your routing options.

The manually placed vias were not really 'connected' as far as Eagle is concerned, even though it fell within the footprint of the fat trace. There needs to be a trace that connects to the center of the via for Eagle to see it as connected. I think here was another 'air wire' somewhere else as well.

See my previous comments about resolving the issues with the QFN package. It the via in the center will still likely throw a DRC. You may Just be able to use a square through-hole pad with a small drill for the center pin. Not sure. I haven't messed with the footprint editor for awhile.

See the attached board file. I played around with it a bit to give you some ideas. I used polygons to route a lot of the power/gnd stuff. If you're going to buy a board WITHOUT solder mask, DO NOT use the flood fills as I have. You'll end up with solder bridges everywhere.