SparkFun Forums

[sternis]

Hi guys

I've been trying for a while now to do something that should be possible to do, but I'm not sure. In short, I'm trying to use my STM32F4Discovery board (or at least the stlinkv2 on it) to program my board with an LPC1769 on. I have tried downloading openocd-0.6.0-rc2 and also using the versaloon branch with swd support. However, I'm not sure which files I should use (cfg-files for interface, target etc). Should I have an openocd.cfg as well (some guides mention this)? Using different combinations of files I get these kinds of errors:
1. Using everything in openocd0.6.0 (specifically the interface stlink-V2)

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 sudo /Users/Sterna/Downloads/openocd/src/openocd -f /Users/Sterna/Downloads/openocd/tcl/interface/stlink-v2.cfg -f /Users/Sterna/Downloads/openocd/tcl/target/lpc1769.cfg

Open On-Chip Debugger 0.6.0-rc2-dev-00001-g9fbfb61 (2012-08-31-18:03)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.sourceforge.net/doc/doxygen/bugs.html
adapter speed: 1000 kHz
adapter_nsrst_delay: 200
Runtime Error: /usr/local/share/openocd/scripts/target/lpc17xx.cfg:54: invalid command name "jtag_ntrst_delay"
in procedure 'script' 
at file "embedded:startup.tcl", line 58
at file "/Users/Sterna/Downloads/openocd/tcl/target/lpc1769.cfg", line 17
at file "/usr/local/share/openocd/scripts/target/lpc17xx.cfg", line 54

2. Using everything (well, mostly the interface ) from versaloon branch (The top line is run straight in the terminal):

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 sudo /usr/local/openocd/bin/openocd -f interface/vsllink-swd.cfg -f lpc1769.cfg

Open On-Chip Debugger 0.6.0-dev-g1981fa8 (2012-09-01-01:02)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.sourceforge.net/doc/doxygen/bugs.html
Warn : must select a transport.
Info : OpenOCD runs in SWD mode
adapter_nsrst_delay: 200
jtag_ntrst_delay: 200
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
500 kHz
Error: Can't find USB JTAG Interface!Please check connection and permissions.
Runtime Error: lpc1769.cfg:62: 
in procedure 'script' 
at file "embedded:startup.tcl", line 58
in procedure 'init' called at file "lpc1769.cfg", line 62

Since I have several versions of oocd (I have like three), it would be appreciated to know if there is any difference in the files I'm supposed to use.
What I HAVE succeded with is something I didn't think would be possible. I have been programming an stm32F103 all summer using a combination of the st-flash util and gdb (using an stlinkv2 and swd) using the load command in gdb. This even loads stuff into flash. I've also tried using this on the LPC1769, and I can debug it (send start/stop commands and examine memory) but when I try to write, it fails immediately.
I also use Mac OSX, so building the software is a little trickier for me, since I can't just go apt-get (I have to use Macports instead, and it doesn't put things in /usr/local/).

Hope anyone can shed some light on my situation.

[sternis]

Hi again

I have worked with this now for a couple of days, and found out some more things.

I tried to create my own config file, and got some action from the programmer. But then I got stuck again. Here is my config file:

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# NXP LPC1769 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, clocked with 4MHz internal RC oscillator

# NXP LPC1769 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
set CHIPNAME lpc1769
#org is 0x4ba00477
#set CPUTAPID 0x4ba00477
set CPUTAPID 0x2ba01477 
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x80000

debug_level 3

transport select stlink_swd

# Main file for NXP LPC17xx Cortex-M3
#
# !!!!!!
#
# This file should not be included directly, rather
# by the lpc1751.cfg, lpc1752.cfg, etc. which set the
# needed variables to the appropriate values.
#
# !!!!!!

# LPC17xx chips support both JTAG and SWD transports.
# Adapt based on what transport is active.
source [find target/swj-dp.tcl]

if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	error "_CHIPNAME not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
if { [info exists CCLK] } {
	set _CCLK $CCLK
} else {
	set _CCLK 4000
}

if { [info exists CPUTAPID] } {
	set _CPUTAPID $CPUTAPID
} else {
	error "_CPUTAPID not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

if { [info exists CPURAMSIZE] } {
  set _CPURAMSIZE $CPURAMSIZE
} else {
	error "_CPURAMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

if { [info exists ENDIAN] } {
	set  _ENDIAN $ENDIAN
} else {
	set  _ENDIAN little
}

if { [info exists CPUROMSIZE] } {
  set _CPUROMSIZE $CPUROMSIZE
} else {
	error "_CPUROMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

#delays on reset lines

#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
stlink newtap $_CHIPNAME cpu -expected-id $_CPUTAPID

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME

# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE

# The LPC17xx devies have 32/64/128/256/512kB of flash memory, managed by ROM code
# (including a boot loader which verifies the flash exception table's checksum).
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
	lpc1700 $_CCLK calc_checksum

# Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
adapter_khz 10

$_TARGETNAME configure -event reset-init {
	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
	# "User Flash Mode" where interrupt vectors are _not_ remapped,
	# and reside in flash instead).
	#
	# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
	# Bit Symbol Value Description Reset
	# value
	# 0 MAP Memory map control. 0
	# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
	# 1 User mode. The on-chip Flash memory is mapped to address 0.
	# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
	#
	# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user

	mww 0x400FC040 0x01
}

# if srst is not fitted use VECTRESET to
# perform a soft reset - SYSRESETREQ is not supported
cortex_m3 reset_config vectreset




proc program_device () {
	reset init
	sleep 50
	flash probe 0
	sleep 50
	flash protect 0 0 last off
	sleep 50
	flash write_image erase unlock "firmware.hex"
	sleep 50
	reset run
	sleep 50
	shutdown
}

init
program_device ()

I got some information on in from this site: https://github.com/mossmann/hackrf/wiki ... -Debugging, but it's somewhat different to what I'm trying to do, but it helped somewhat. The error I get is related to the ID. When I run the script I get the following error:

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Error: 175 811 stlink_interface.c:79 stlink_interface_init_target(): stlink_interface_init_target: target not found: idcode: 0x2ba01477

And when I change the CPUTAPID to 0x2ba01477, I get the following error:

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Assertion failed: (jtag_trst == 0), function jtag_checks, file core.c, line 339.
./ProgramHex: line 6: 42257 Abort trap: 6

Where ProgramHex is my script file for programming (it runs the call to openocd). I send in the stlink-v2.cfg to the call to openocd. Using both of the configurations, I seem to get some sort of contact with the stlink, because the LED on the board changes to green.

Anyone know what it would be or have a solution to the problem or could perhaps tell me more?

[ntfreak]

It should be possible but you are getting the configs all mixed up.
The stlink is a unique device and its config does not follow the normal OpenOCD scheme

try something like the following - not tested and does need cleaning up.

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set _CHIPNAME lpc1769

source [find interface/stlink-v2.cfg]
transport select stlink_swd

stlink newtap $_CHIPNAME cpu -expected-id 0x1ba01477

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME stm32_stlink -chain-position $_TARGETNAME

$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000

set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 4000 calc_checksum

$_TARGETNAME configure -event reset-init {
    # remap flash to 0x0
    mww 0x400FC040 0x01
}

also do not use 'flash protect' with the stlink - it is not supported and may cause strange problems.

Cheers
Spen

[sternis]

Hi again

Thanks for the help Spen. I got it working now. The script you posted needed some small changes though:
You had the wrong ID: It should be a 2 instead of a 1 in the beginning.
Also, when running the script, it actually does nothing (it doesn't crash, but it just sits there), so I added the proc program_device and an init and a call to this proc at the end and it worked like a charm!

The complete script is the following:

Code: Select all

set _CHIPNAME lpc1769

transport select stlink_swd

stlink newtap $_CHIPNAME cpu -expected-id 0x2ba01477

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME stm32_stlink -chain-position $_TARGETNAME

$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000

set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 4000 calc_checksum

$_TARGETNAME configure -event reset-init {
    # remap flash to 0x0
    mww 0x400FC040 0x01
}

# 4MHz / 6 = 666kHz, so use 500
adapter_khz 500

proc program_device () {
	reset init
	sleep 50
	flash probe 0
	sleep 50
	flash protect 0 0 last off
	sleep 50
	flash write_image erase unlock "firmware.hex"
	sleep 50
	reset run
	sleep 50
	shutdown
}

init
program_device ()

Also, the ProgramHex-code I mentioned earlier looks like this:

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#!/bin/sh

cp Release/testArm_summon.hex firmware.hex

# For stlink-v2 found on the STM32F4Discovery
/Users/Sterna/Downloads/openocd/src/openocd -f stlink-v2.cfg -f lpc1769_3.cfg 

rm firmware.hex

I keep both the file lpc1769_3.cfg and stlink-v2.cfg in the same folder as the script placed in the project-folder of my eclipse project (called testArm_summon). This is because I have several instances of openocd on my computer, and I want to make sure it picks the correct files. Also, the first row (#!/bin/sh) is there so that OSX can run this script correctly.

[ntfreak]

Glad it is working - it was not meant todo anything.
Also try not to use flash unlock or protect off if not required - it is a waste of cycles.

Spen

[Karibe]

I want to use this combo for debugging freescales KL25Z board, how to write the script and the Openocd config files for the Serial Wire Debug (SWD) interface on the board