- Mon Mar 14, 2011 4:40 am
#122708
Hello forum members,
I am using MSP430F5419A and trying to configure the internal watchdog. The clock source for WDOG is SMCLK and equals 1MHz. I have configured WDOG to @ 8 sec timeout and refreshing it timely. The code works fine without any reset.
I am using WDTIFG flag from SFRIFG1 to detect if WDOG reset has triggered. When I remove the timely refresh for the WDOG, the code resets after @ 8 sec but if I read the SFRIFG1 register, it displays OFIFG flag as set instead of WDTIFG. What could be the reason? I am using CrossStudio compiler and using TI MSP430-FET debugger to observe the registers. Has anyone experienced similar? What other configuration like interrupt etc is required to be done? I tried enabling WDT interrupt (SFRIE1 |= WDTIE) but this also results the same.
Your earliest help in this regard will be highly appreciated. Thanks in advance.
Mike.
I am using MSP430F5419A and trying to configure the internal watchdog. The clock source for WDOG is SMCLK and equals 1MHz. I have configured WDOG to @ 8 sec timeout and refreshing it timely. The code works fine without any reset.
I am using WDTIFG flag from SFRIFG1 to detect if WDOG reset has triggered. When I remove the timely refresh for the WDOG, the code resets after @ 8 sec but if I read the SFRIFG1 register, it displays OFIFG flag as set instead of WDTIFG. What could be the reason? I am using CrossStudio compiler and using TI MSP430-FET debugger to observe the registers. Has anyone experienced similar? What other configuration like interrupt etc is required to be done? I tried enabling WDT interrupt (SFRIE1 |= WDTIE) but this also results the same.
Your earliest help in this regard will be highly appreciated. Thanks in advance.
Mike.