MSP430x4xx - 921600 UART & 32Ksps SD16 Communication

[engrforever]

IDE and Software details:
IAR Workbech MSP430
MCU: MSP430FE427
Board 1: http://www.sparkfun.com/commerce/produc ... ucts_id=52

Board 2: http://www.ghielectronics.com/details.php?id=1&sid=2

I am trying to sample the SD16 ADC module at the highest rate with "SD16CCTL2 |= SD16OSR_32", which provides me with approximately 32Ksps. The MCU is utilizing the basic 32Khz crystal and utilizing the DCO, I use an MCLK of approximately 8 Mhz.
I need to send the two bytes genereated by the SD16 to a secondry board for logging, via UART. Based on my calculations, for 32Ksps, I will need a minimum baudrate of 625,000. The baud rate I am trying to communiate is 921600.

I am having difficulty transmitting data accurately via UART at 921600. Please advice how I can accomplish this or any better way.

[bmckenney]

If you're using the DCO to get an accurate clock, you're (almost
certainly) using the clock modulator. The modulator (intentionally)
introduces jitter into the clock sufficient to drive a (PC) UART crazy.

The jitter adds up to 0 every 32 clocks, so to get reliable transmission
you need to limit your bit rate to F_DCO/32 (at 8MHz->250kbps).

[engrforever]

....
The jitter adds up to 0 every 32 clocks, so to get reliable transmission
you need to limit your bit rate to F_DCO/32 (at 8MHz->250kbps).

bmckenney,

I am not sure if I clearly understand.

Are you suggesting I can only communicate well at 250kbps?
Where do I F_DCO/32? The MSP430FE427 does not have a 32 divider on the FLL module
Would using a higher crystal than the 32Khz help?

Thank you for your time!

[bmckenney]

Are you suggesting I can only communicate well at 250kbps?

Above that and the Modulator jitter will confuse the receiver. Probe
your Tx line with a scope and you'll see what I mean.

Where do I F_DCO/32? The MSP430FE427 does not have a 32 divider
on the FLL module

Just set the USART bit rate divider so it divides the DCO (including any
SMCLK divisor) by something >=32, Which at 8MHz means a bit rate <=250kbps.
(It looks(?) as though you're actually using the FLL at 7.37..MHz, if so
max <=230.4kbps.)

Would using a higher crystal than the 32Khz help?

The modulator is part of DCO operation. I think (I haven't tried it) you
can use e.g. a 7.37..MHz crystal through LFXT1 and bypass the FLL/DCO, but
I suspect(?) that isn't what you had in mind.

[engrforever]

The FLL setup I am using to achieve 8Mhz is as below:

SCFI0 |= FN_3; // Set DCO operating range
SCFQCTL = 122; // (121+1) x 32768 x 2 = 7.99 Mhz
FLL_CTL0 = DCOPLUS + XCAP14PF; // DCO+ set so freq = xtal x D x N+1

I shut turned of my clock init function and scoped the default generation: 1.0485767 Mhz.

How much should I expect the clock to vary (keeping in mind I am using a 16 bit adc and trying to use UART at high baud rates)?

Just looking the clk signal, it was moving from 1.023, 1.044, 1.073 Mhz. (using the digital probes on Agilent MSO654A.)

[bmckenney]

SCFQCTL = 122; // (121+1) x 32768 x 2 = 7.99 Mhz

Shouldn't this be: (122+1)x... = 8.06MHz? Which is about what you're
seeing.

Just looking the clk signal, it was moving from 1.023, 1.044, 1.073 Mhz.

This is the DCO Modulator at work. The DCO ratio is about 6%, so +/-2.5%
seems not too far off.