I've used the PIC16, 18, dspic 24, 30, and 33 chips but the pic32 is still new to me. I'm trying to understand the interrupt structure on the chip and here's what I think I've understood..
1) The mips r4k core has no interrupt controller internally, so an "external" (same die) interrupt controller is implemented.
2) The interrupt controller has two modes of operation - single vector and multi vectored. As I understand these, single vector is similar to the PIC16/18 mode of operation whereby the users code is responsible for determining which interrupt has fired and taking things from there. In multi vectored mode the interrupt controller decodes this information and presents the correct ISR address to the processor.
3) While I'm interested in multi vectored mode it seems that there are still interrupts that overlap. For example on the PIC32MX695F512L, there are "A" and "B" serial (RS232/SPI/I2C) interfaces were the one type (A/B) has an interrupt vector all to itself for each of RS232, SPI and I2C, while the other shares one interrupt between 2-3 serial peripherals.
Am I reading this properly? Also if I was to write an ISR for each of them would the compiler generate the testing/re-vectoring code to handle this?
Sorry for the long question, and please let me know if I need to clarify it.
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