- Tue May 27, 2008 10:47 pm
I'm tossing some ideas around for a circuit, eventually I'll post it or if anyone knows of a site where a collaborative effort can be done it'll be added there for comment and improvement.
Just need some sanity checking. Can anyone check their interpretation of the datasheet on my assumptions please?
1) The device clock is via the EXTCLK pin, and the internal clock rate can be set with the PLL to various settings via I2C commands
2) When the device outputs a JPEG file (or other image formats) data is presented to the D0..D7 pins and is valid on the rising edge of the DCLK pin which is an output of the device. A data frame or jpeg frame is indicated by a high on the VBLK pin. The HBLK pin indicates the device pausing while it is doing JPEG compression.
3) The DCLK pin is actively clocking along, even when the device isn't doing anything, data is only valid when the VBLK pin is high.
4) We can just take the JPEG output of the imager chip as a valid JPEG file without further processing (assuming we can get the data to a memory card).
So from these assumptions we could build a circuit that takes the VBLK pin and enables a SRAM chip. The DCLK pin can then be used to perform a write enable operation and also clock a binary counter chip (or chips depending on the address space needed). This would automatically clock the data into the ram chip for later retrieval by the micro.
To complete the circuit we need a way to disengage output operations from the imaging chip so the micro can look at the ram. The micro could control the reset of the binary counter chip to reset to the start of the frame, then take over (possibly by a little extra logic) the clocking of the counter, reading it and writing to the SD card as needed.
I can't see a pin to disable output from the imager....so I presume there is an I2C command to do it...does anyone have an idea where the command set for the chip is? I can see a list of registers, but no list of what the register values should be for different operations.
Also any suggestions on a suitable oscillator frequency to clock the imaging chip with?
If the assumptions are wrong, please indicate this and any suggestions you might have.