I'm tossing some ideas around for a circuit, eventually I'll post it or if anyone knows of a site where a collaborative effort can be done it'll be added there for comment and improvement.
Just need some sanity checking. Can anyone check their interpretation of the datasheet on my assumptions please?
1) The device clock is via the EXTCLK pin, and the internal clock rate can be set with the PLL to various settings via I2C commands
2) When the device outputs a JPEG file (or other image formats) data is presented to the D0..D7 pins and is valid on the rising edge of the DCLK pin which is an output of the device. A data frame or jpeg frame is indicated by a high on the VBLK pin. The HBLK pin indicates the device pausing while it is doing JPEG compression.
3) The DCLK pin is actively clocking along, even when the device isn't doing anything, data is only valid when the VBLK pin is high.
4) We can just take the JPEG output of the imager chip as a valid JPEG file without further processing (assuming we can get the data to a memory card).
So from these assumptions we could build a circuit that takes the VBLK pin and enables a SRAM chip. The DCLK pin can then be used to perform a write enable operation and also clock a binary counter chip (or chips depending on the address space needed). This would automatically clock the data into the ram chip for later retrieval by the micro.
To complete the circuit we need a way to disengage output operations from the imaging chip so the micro can look at the ram. The micro could control the reset of the binary counter chip to reset to the start of the frame, then take over (possibly by a little extra logic) the clocking of the counter, reading it and writing to the SD card as needed.
I can't see a pin to disable output from the imager....so I presume there is an I2C command to do it...does anyone have an idea where the command set for the chip is? I can see a list of registers, but no list of what the register values should be for different operations.
Also any suggestions on a suitable oscillator frequency to clock the imaging chip with?
If the assumptions are wrong, please indicate this and any suggestions you might have.
I have this cam writing frames directly into an SRAM chip I pulled off an old hard drive. Which I then read with an ATMega.
I currently have the cameras EXT CLK line connected to a 12MHz crystal clock. Higher clock rates are possible it will depend on the write time for the SRAM. I just happened to have some 5V 12MHz modules laying around. At 12MHz I am capturing 14.65 fps.
The SRAM address lines are connected to 74HC161 binary counters which are clocked by the cameras DCLK line.
The counters active low reset lines are connected to the cameras VD so that each new frame resets the SRAM back to address 0.
The counters Count Enable is connected to the cameras HD so that the counters only advance during a valid line. The counters will pause during horizontal/vertical blanking.
DCLK is also fed to the SRAM Write Enable line which is active low.
The 8 bit camera data bus is connected to the SRAM data bus via a 74HCT574 latch. Using an HCT here acts as an a bit logic level converter. The latch is active on a rising edge clock so the cameras DCLK is used to drive the latch clock.
The counters control lines are fed into the A bus of a 74HC157 1 of 2 4-bit data switch. The B bus is connected to the ATMega. The bus selection line is connected to the ATMega which allows it to control if the clocks and SRAM are driven automatically or by the ATMega.
When the SRAM is being driven automatically the following happens:
- VD resets all counters to 0 which in turn sets the SRAM to address 0.
- HD rises when the first byte of pixel data is available on the cameras data bus enabling DCLK to advance the counters.
- DCLK rises and the first pixel is latched via the 74HC574 onto the SRAM data bus.
- DCLK falls and the SRAM Write Enable is active which writes the byte latched by the 74HC574 into the first SRAM memory location.
Bytes are successively written into SRAM until HD falls at the end of the line at which time the counters pause until HD rises signaling the start of the next line.
After a complete frame is written into SRAM, VD will fall causing the timers to reset and the whole process repeats itself at a nice high frame rate.
An 8 bit I/O port on the ATMega is connected to an 74HC245 8-bit bus tranciever. The enable is connected to the 74HC157 select line and to the 74HC574 enable via a 74HC04 inverter so that only the camera or the ATMega is connected to the SRAM data bus at one time.
Changing the select line of the 74HC157 from "SAMPLE" to "HOLD" gives control of the counters reset and clock lines over to the ATMega. My dump frame function then just resets the counters, reads a byte from SRAM, sends it out the serial port, clocks the counters to the next address and repeats for the length of the frame.
This allows me to capture frames at a high frame rate and then use a low speed mcu to read/analyze the frame at it's own pace without worrying about trying to keep up with DCLK in some tightly woven assembly function.
I have been able to dump frames to my pc from all modes from 320x240 down. As long as you have enough counters and SRAM to cover the resolution you want to run in it works pretty good so far. I happen to be using a CYM1464, 512k x 8bit SRAM with 25ns r/w but you could scale down to a 32k x 8bit SRAM if you stay in the low resolutions.
I'm also thinking of dividing the VD in half so that two sequential frames are written to the SRAM making it easy to compare frames. There is also the possibility of connecting the counter presets to the ATMegas external SRAM interface so that it can randomly access frame data instead of sequentially, however all the stuff I want to do with the data involves reading the data sequentially so I'm not sure how much advantage this would hold.
Using surface mount versions of the mentioned chips would make this a fairly small package.
A lot of fun for a $10 camera and a hand full of dime-a-dozen parts from all those past grab bags
All registers at default values except AWB disabled under a 40w incandescent light