TTL NAND gate / voltages

A place to hang out and chat with other like minded tinkerers

Moderator: phalanx

Post Reply
Posts: 1
Joined: Sat Nov 25, 2017 10:50 am

TTL NAND gate / voltages

Post by Sandwich » Sat Nov 25, 2017 11:19 am

Hi! I'm new to the forum and am a novice with electronics. I've gotten stuck... I'm trying to understand the behavior of transistors Q2 and Q4 in the classic TTL NAND gate. Any advice is appreciated!

I understand that an NPN transistor in cut-off mode has low voltage at its base, and high voltage at the collector and emitter. If that's the case, I don't understand why Q4 is cut-off, whenever Q2 is cut-off. Q4's base is connected to the high-voltage emitter of the cut-off Q2, I would think that would cause Q4 to saturate? I'm missing something fundamental here!

Specifically I'm studying Albert Malvino's book "Digital Computer Electronics" and am trying to supplement my understanding via several other sources.

Thank you!

Post Reply