Opensource FPGA design toolflows

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john_t_eaton
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Joined: Sat Apr 18, 2015 4:54 pm

Opensource FPGA design toolflows

Post by john_t_eaton » Sat Jun 06, 2015 9:28 am

I would like to start a discussion on design entry toolflows for fpgas and asics. I know that there was a previous discussion here that centred on HDL v Schematic but I think it missed point. Any entry method must eventually deliver an hdl net list and whether you write the code in hdl or enter it via a schematic editor doesn't matter. You really want to give the designer the option to use either one depending on the module.

No what I would like to discuss is a far more serious problem that this industry has been ignoring for 40 years: Design for Reuse.

Design reuse is essential for this industry to survive. If you start a new design today then you will probably have 60-80% of the code finished on the day that you begin. If not then you will likely take many extra years to finish it. We have always reused code from previous chips or purchased from outside vendors and we will need to do more of this in the future.

The problem is that we really do a lousy job when creating modules for other designers to use in their chips. Imagine a world where we did not have a standard for putting discrete components on tape and reel. Each vendor would have their own system and a manufacturer would have to deal with receiving several different ones and would have to create new solutions almost every day. That is the world that IC design is currently in. The manufacturing world came together and published standards so that everyone knew what to deliver and what to expect. The IC world has yet to create such a standard and it is chaos.

There are studies that show that for each dollar that we spend on EDA tools that we will spend three dollars making those tools all work together. When you design a chip you will spend a huge amount of time writing and debugging your tool flow scripts and every time you receive a new component you find that something breaks and you have to go in a hack in a fix.



The weird thing is that an IC design tool flow is a ideal problem for an opensourced solution. We have a lot of engineers writing scripts that all do essentially the same thing. Nothing in these scripts are company secrets. We would all do a better job if we would share our efforts and create a opensourced toolflow for IC and fpga design entry. There are enough free EDA tools out there that you can stitch these together with a toolflow and wind up with a totally free and complete design entry system.

We need to start talking about what we need for a design standard and what the toolflow would have to accomplish. Tell me what you don't like about your current design tools and what we could do to fix it.


I do manage an opensource toolflow project on opencores.org and sourceforge.net called socgen. It currently contains some toolflows and sample designs. You can create an embedded system. simulate with icarus and/or verilator, get code coverage from covered and synthesize for a Digilent Nexys2 board. I invite everyone to download this project and try it out. Please let me know if you have success or failure.



John Eaton

z3qmtr45@gmail.com

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