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[cospan]

I've been working on a project for a couple of years now. It's an FPGA development board in the form factor of an Arduino... I know I know Papilio... but I swear I had the idea independent of it a couple of years ago. The design is similar in that you can power it, program it and communicate with it over USB and it has 8MB of memory. Here's the difference. I spent a long time making the development of an FPGA based project as easy as possible.

I use Python scripts to glue together Verilog cores. The format of every project has the same feel in that you write and debug small Verilog cores and you use either configuration files or a GUI to glue together those cores. Here is a screen shot of the GUI used to build an entire FPGA image:



There are more screen shots on this wiki page:

http://wiki.cospandesign.com/index.php?title=Nysa

Although they are pretty pictures, I'm sure you would like to know what you can do with it... well... A LOT!

there are already cores that you can visually glue together for all the low speed peripherals including:

UART

SPI: Here's a Digilent OLED PMOD with my logo


I2C: Here's a I2C DAC attached to the one of the headers

(Sorry I don't have a picture of the Oscilloscope trace, I'll have to setup the project again later and take a picture or video of it)

Also a logic analyzer core, here is a logic analyzer capture that I was using to debug the SDRAM core. It outputs VCD files that you can read with gtkwave
http://wiki.cospandesign.com/index.php? ... _Image.png

Here is where Dionysus separates itself from an Arduino/microcontroller board: I spent a lot of time developing the SDRAM core and FTDI Parallel FIFO interface to acheive a relatively high level of throughput between the host computer and Dionysus, it's so fast you can stream music and video (I haven't tested the max framerate on my LCD yet but I am working on it)

So here are the higher throughput projects that employ a DMA style interface, where the host either reads or writes data to memory as apposed to directly to a core

I2S: Unfortunately I can't show sound but you can play audio through the Digilent I2S PMOD


Camera: The TCM8230MD is an awesome little camera, here is an image from it:
(I have to switch to URLs because the Sparkfun Forum or my wiki is not happy loading all these images)
http://wiki.cospandesign.com/index.php? ... :Image.png

Here's a picture of the camera shield:
http://wiki.cospandesign.com/index.php? ... Shield.png

LCD: I've only been getting static images onto the LCD but I am working on a PyQt Video output to write video to the LCD and read images from the Camera
http://wiki.cospandesign.com/index.php? ... 003500.jpg
(Sorry for the terrible quality of the image but I haven't played around with the settings enough to reduce the LCD backlight)

The user interface is a Python API which allows users to read and write registers and memory with simple commands like

Code: Select all

        
def set_control(self, control):                                                                              
        """set_control                                                                                           
                
        write the control register                                                                               
        
        Args:
          control: 32-bit control value                                                                          
        
        Return:
          Nothing
        
        Raises:                                                                                                  
          NysaCommError: Error in communication
        """ 
        self.o.write_register(self.sf_cam_id, CONTROL, control)   

The script that generates the FPGA image also generates a ROM core that can be read by the host so software users can simply read the ROM to find out what's is on the FPGA, here is a dump of the Dionysus Unit tester script that I use to exercise various cores NOTE: the tester annotates the ROM file:

Code: Select all

cospan@silk:~/Projects/olympus/host$ ./test_dionysus.py 
starting...
Reading DRT
Printing DRT:
 DRT:

0004C594:Version: 0004 ID Word: C594
00000004:Number of Devices: 4
00000000:String Table Offset (0x0000 == No Table)
00000000:Reserverd for future use
00000000:Reserverd for future use
00000000:Reserverd for future use
00000000:Reserverd for future use
00000000:Reserverd for future use
 Devices:

 Device 0
00000001:Device Type: GPIO
00000001:Device Flags:
	0x00000001: Standard Device
01000000:Offset of Peripheral Device:  0x01000000
00000005:Number of Registers :         0x00000005
00000000:Reserved for future use
00000000:Reserved for future use
00000000:Reserved for future use
00000000:Reserved for future use

 Device 1
00000003:Device Type: I2C
00000001:Device Flags:
	0x00000001: Standard Device
02000000:Offset of Peripheral Device:  0x02000000
00000007:Number of Registers :         0x00000007
00000000:Reserved for future use
00000000:Reserved for future use
00000000:Reserved for future use
00000000:Reserved for future use

 Device 2
0000000D:Device Type: Camera
00000001:Device Flags:
	0x00000001: Standard Device
03000000:Offset of Peripheral Device:  0x03000000
00000008:Number of Registers :         0x00000008
00000000:Reserved for future use
00000000:Reserved for future use
00000000:Reserved for future use
00000000:Reserved for future use

 Device 3
00000005:Device Type: Memory
00010003:Device Flags:
	0x00000001: Standard Device
	0x00010000: Memory Device
00000000:Offset of Memory Device:      0x00000000
007FFFFF:Size of Memory device:        0x007FFFFF
00000000:Reserved for future use
00000000:Reserved for future use
00000000:Reserved for future use
00000000:Reserved for future use
 Unit Test
Found 4 slaves 
Searching for standard devices...
Found GPIO
testing GPIO @ 1
Testing output ports (like LEDs)
Flashing all the outputs for one second
Set all the ports to outputs
Set all the values to 0
Reading inputs (Like buttons) in 2 second
Read value: 0x0
Reading inputs (Like buttons) in 2 second
Read value: 0x0
Testing Interrupts, setting interrupts up for positive edge detect
Waiting for 5 seconds for the interrupts to fire
Found a memory device
testing memory @ 3
Memory is on Memory bus
Clearing memory
Testing short write
Testing short read
Testing a write/read at the end of memory
writing to memory location 0x007FFFF7
	writing a value: array('B', [170, 187, 204, 221, 85, 102, 119, 136])
reading from memory location 0x007FFFF7
	reading: array('B', [170, 187, 204, 221, 85, 102, 119, 136])
single read time: 0.000013
Memory size: 0x800000
Writing 8388608 bytes of data
Reading 8388608 bytes of data
Comparing values
Length of outgoing:  0x00800000
Length of incomming: 0x00800000
Memory test passed!

The read times are inaccurate.

The code is split up into three sections and it's on Git

https://github.com/CospanDesign/nysa

cbuilder (Core builder): to build and test Verilog cores you can use a script to generate a sample Verilog core that can be immediately added to an image
ibuilder (Image Builder): use configuration files and/or the GUI to build entire FPGA Images
host: Host side software, or the Python interface

The project is still a work in progress but now that the LCD, Camera and I2S are working I'm going to spend time refining and refactoring.

The software platform can even be migrated to work with any FPGA board including the Papilio and all the kitchen sink boards on Digilent.

I am working hard preparing to launch a Kickstarter to start producing Dionysus..es (plural) and I hope to find out if there is interest in this


Dave