18F25K20 on change interrupt

Find out how to setup your programmer's software and how to solve many common problems.

Moderator: phalanx

Post Reply
Posts: 1
Joined: Wed Jun 28, 2017 8:07 am

18F25K20 on change interrupt

Post by Nikola010 » Wed Jun 28, 2017 8:10 am

When i configure on port change interrupt, first time when it happens, it keeps running into interrupt over and over again. The moment it comes into main program interrupt happens again without any change on port. Why is this happening?

Code: Select all

void interrupt(){
      INTCON.RBIF = 0;
      PORTC.RC0 = !PORTC.RC0;
      PORTC.RC1 = !PORTC.RC1;
void main() {
        OSCCON.IRCF0 = 1;
     OSCCON.IRCF1 = 1;
     OSCCON.IRCF2 = 1;
     OSCCON.SCS1 = 0;
     OSCCON.SCS0 = 0;

        TRISB = 255;
        TRISC = 0;
        PORTC = 0;
        PORTC.RC0 = 1;
        PORTC.RC0 = 0;
        PORTC.RC0 = 1;
        INTCON.RBIE = 1;
        INTCON.RBIF = 0;
        IOCB = 255;
        INTCON2.RBIP = 1;
        INTCON.GIE = 1;

User avatar
Non-SFE Guru
Posts: 1983
Joined: Sun Nov 30, 2003 8:57 am
Location: Candia, NH

Re: 18F25K20 on change interrupt

Post by phalanx » Thu Jun 29, 2017 5:29 am

Hi Nikola,

Your answer can be found in section 10.3.2 of the datasheet. Basically you need to do a read or write to PORTB to clear the mismatch status. The PIC keeps track of the prior value of the interrupt on change pins for the purpose of generating the interrupt and a read or write to the port will update their current state. If the mismatch still exists when you exit your ISR, the PIC will immediately interrupt again due to it thinking you had a change on one of your pins.
The user, in the Interrupt Service Routine, can clear the interrupt in the following manner:

a) Any read or write of PORTB to clear the mismatch condition (except when PORTB is the source or destination of a MOVFF instruction).

b) Clear the flag bit, RBIF.

A mismatch condition will continue to set the RBIF flag bit. Reading or writing PORTB will end the mismatch condition and allow the RBIF bit to be cleared. The latch holding the last read value is not affected by a MCLR nor Brown-out Reset. After either one of these Resets, the RBIF flag will continue to be set if a mismatch is present.

Post Reply