- Wed Aug 29, 2007 7:51 am
#34430
Hello,
I want to make the layout for two sdrams connected to an ARM9 controller. I calculated a min. hold margin and min. setup margin - both with 2ns. The clk clock is 80 MHz and the rise time is about 2.5ns.
Could you explain to me how long the longest trace and the shortest trace could be? The trace for the clk is about 60mm long. Within which time must the other signals come to the sdram?
How big can be the difference of phase between the specific signals? And how can I calculate this phase shift?
best regards
saoirse
I want to make the layout for two sdrams connected to an ARM9 controller. I calculated a min. hold margin and min. setup margin - both with 2ns. The clk clock is 80 MHz and the rise time is about 2.5ns.
Could you explain to me how long the longest trace and the shortest trace could be? The trace for the clk is about 60mm long. Within which time must the other signals come to the sdram?
How big can be the difference of phase between the specific signals? And how can I calculate this phase shift?
best regards
saoirse