SparkFun Forums

[saoirse]

Hello,

I want to make the layout for two sdrams connected to an ARM9 controller. I calculated a min. hold margin and min. setup margin - both with 2ns. The clk clock is 80 MHz and the rise time is about 2.5ns.

Could you explain to me how long the longest trace and the shortest trace could be? The trace for the clk is about 60mm long. Within which time must the other signals come to the sdram?

How big can be the difference of phase between the specific signals? And how can I calculate this phase shift?

best regards
saoirse

[ke7eha]

Delay times in electronics are all related to c, the speed of light. For all practical purposes:

c = 3.0 x 10^8 m/s

a massive number. That's the velocity of EM waves through free space. Granted, the speed of e- in copper is probably a bit slower than that, it is still an EM wave, and thus has a similar speed.

The length of the traces should be very close to one another, for timing and impedance and stuff like that. I would just run the traces in parallel directly from the ARM9 to the SDRAM chip, like is done for JTAG. This wil;l avoid timing issues and look freakin' sweet too.

If you do run into length issues, you can always route in loops or longer paths if you so choose. An example of this type of routign is found on GPU card, such as this one: http://flickr.com/photo_zoom.gne?id=254400544&size=l
this photo shows a GeForce 6600 card, with routing for timing on the board, as well as a dusty card. My friend Jasper took the photo when I was re-seating the heatsink. You can find things like that all over in critically timed items. In reality, I do not believe you'll have to be that exact, but be as exact as you think you need to be, and check your numbers.