SMD QFP in 'smd-ipc' library fails DRC?

Questions relating to designing PCBs

Moderator: phalanx

Post Reply
silic0re
Posts: 349
Joined: Wed Apr 26, 2006 5:35 pm

SMD QFP in 'smd-ipc' library fails DRC?

Post by silic0re » Tue Jul 31, 2007 10:06 pm

Hi there,

I'm a new user to Eagle, and am in the process of designing a board that makes use of a few components with some large numbers of pins (~100). I added these new devices into a library, and made the schematics, but just used the SQFP-S-14x14-100 package already defined in the 'smd-ipc' library. Unfortunately this package seems to fail the DRC check, as the space between pads looks to be less than 8 mil. My question is, what is generally done in this situation? Do you make your own package with tiny traces, or just use these existing packages somehow?

thanks for your help,
(especially to a new board maker!)
silic0re

User avatar
leon_heller
Support Volunteer
Posts: 5734
Joined: Sun May 01, 2005 11:20 am
Location: St. Leonards-on-Sea, E. Sussex, UK.

Post by leon_heller » Wed Aug 01, 2007 12:32 am

Why not change the DRC rules to those acceptable to your board supplier?

Leon
Leon Heller
G1HSM

Philba
Support Volunteer
Posts: 2503
Joined: Sun Feb 13, 2005 11:33 pm
Location: Seattle

Post by Philba » Wed Aug 01, 2007 9:26 am

perhaps you don't understand the DRC concept. The default DRs are just a guess on eagle's part. You need to understand what your board provider can do and adjust your DRs to that.

In the case of SFE, they've said that they can probably handle .2mm clearance (which is slightly less than 8 mil). Check the batchPCB section, it's been discussed multiple times. Their board house has some what better tolerances than SFE has set in their DRCbot. Of course, this is assuming that your part has .5mm pitch pads (.2mm clearance, .3mm wide pads).

On the subject of using eagle library parts - trust but verify. You don't know who made that part. Are you willing to risk a PCB cycle with out making sure it's right?

silic0re
Posts: 349
Joined: Wed Apr 26, 2006 5:35 pm

Post by silic0re » Wed Aug 01, 2007 11:51 am

Sorry, perhaps I didn't make my issue clear. I'm not using the default DR's, but have set them to what batchPCB would be capable of creating (including 8mil spacing between pads). Using BatchPCB's design rules with the stock QFP-14x14-100 package (0.5mm pitch pins) in the 'smd-ipc' library included with Eagle, this package fails the clearance checks. I suppose, to rephrase my original question, for those who have used QFP's with a 0.5mm pitch with BatchPCB, what have you used for the package? How have you handled this issue?

I did learn a little more about the issue from your suggestion that the pads are infact 0.2mm clearance. If I change the DR's to 0.2mm clearance instead of 8 mil, the board passes. Is this a big deal? If I submit the board, will it tank on the DRC? (Would it be easier to remake a QFP package with 8 mil clearance instead of 0.2mm?).

thanks for any thoughts,
silic0re

busonerd
Ex-SFE Guru
Posts: 700
Joined: Fri Jun 17, 2005 11:08 am
Location: Vancouver, BC, Canada
Contact:

Post by busonerd » Wed Aug 01, 2007 11:54 am

You can sneak it by DRC. We actually have the bot checking at 6.9 mils.

We prefer people to stay as close to 8 mils as possible, or larger, but if you need to go under that down to 7 on occasion, thats ok.


Cheers,

--David Carne

silic0re
Posts: 349
Joined: Wed Apr 26, 2006 5:35 pm

Post by silic0re » Wed Aug 01, 2007 12:04 pm

Thanks for your help. I think I'll try to make a package with larger clearances, as it seems better to error on the side of caution. Especially for onces first board. :)

busonerd
Ex-SFE Guru
Posts: 700
Joined: Fri Jun 17, 2005 11:08 am
Location: Vancouver, BC, Canada
Contact:

Post by busonerd » Wed Aug 01, 2007 12:12 pm

We can definitely fab that low.. Our fab just gets annoyed with it if we do it to often ;).

However, feel free to do it for important chips / etc. Just avoid it for the entire board if possible.

Cheers,

--David Carne

Post Reply