Design failed DRC

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denisbest
Posts: 25
Joined: Thu Jun 21, 2007 9:38 pm
Location: Buffalo Grove, IL

Design failed DRC

Post by denisbest » Thu Jun 21, 2007 9:46 pm

Hi,

I'm trying to use the BatchPCB service for the first time and my design can't pass the DRC test. I made "clearance" and "distance" settings be 10mil or higher. The images, returned by bot, are all green and are not highlighted by orange or purple which are the signals of errors. What should I do to fix it? :(

Log file:

unmatched 274X paramblock OFA0B0 - len 6
Macro Name = OC8
Macro Consuming 5,1,8,0,0,1.08239X$1,22.5 [2]
PUSH 1.000000
PUSH 8.000000
PUSH 0.000000
PUSH 0.000000
PUSH 1.082390
FETCH 1
MUL
PUSH 22.500000
PRIM 5
Parse_OK
Arg: 0.0520
Looking up macro OC8 [0x54f140]
Beginning GCODE run
Ending GCODE run
Created 359 polygons
Found 0 errors
Partitioning....
Grouping...
Distance testing
MergeCount: 260
tests: 17541
Board boundaries: Rect: [0.075200,0.126400] -> [2.312200,2.276000], w: 2.237000, h: 2.149600
Found 99 groups
lengthdb size 0
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow[/code]

denisbest
Posts: 25
Joined: Thu Jun 21, 2007 9:38 pm
Location: Buffalo Grove, IL

An idea...

Post by denisbest » Thu Jun 21, 2007 9:59 pm

Hm, I think I'm getting an idea. Eagle said "DRC no errors", but ViewPlot highlighted 13 violations of the 8/8 rule. I will try to fix it (don't know how)..

denisbest
Posts: 25
Joined: Thu Jun 21, 2007 9:38 pm
Location: Buffalo Grove, IL

Post by denisbest » Thu Jun 21, 2007 10:28 pm

I tried hard and eliminated all the errors in the viewer. However, DRC nazi denied my request due to the spacing, I believe. How do I fix this?


unmatched 274X paramblock OFA0B0 - len 6
Macro Name = OC8
Macro Consuming 5,1,8,0,0,1.08239X$1,22.5 [2]
PUSH 1.000000
PUSH 8.000000
PUSH 0.000000
PUSH 0.000000
PUSH 1.082390
FETCH 1
MUL
PUSH 22.500000
PRIM 5
Parse_OK
Arg: 0.0520
Looking up macro OC8 [0x54f140]
Beginning GCODE run
Ending GCODE run
Created 360 polygons
Found 0 errors
Partitioning....
Grouping...
Distance testing
MergeCount: 262
tests: 17706
Board boundaries: Rect: [0.075200,0.126400] -> [2.312200,2.276000], w: 2.237000, h: 2.149600
Found 98 groups
lengthdb size 0
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC space fail: [0x55ed70 0x567010] 0.003723 - 0.006900
DRC space fail: [0x5693b0 0x56eba0] 0.005000 - 0.006900
DRC space fail: [0x569450 0x56eba0] 0.005414 - 0.006900
DRC space fail: [0x56eba0 0x5693b0] 0.005000 - 0.006900
DRC space fail: [0x56eba0 0x569450] 0.005414 - 0.006900

denisbest
Posts: 25
Joined: Thu Jun 21, 2007 9:38 pm
Location: Buffalo Grove, IL

Post by denisbest » Fri Jun 22, 2007 10:42 am

Can someone please send me their BatchPCB-complient Design Rules file (*.dru)? Please send to: gnuneman_at_yahoo_com

busonerd
Ex-SFE Guru
Posts: 700
Joined: Fri Jun 17, 2005 11:08 am
Location: Vancouver, BC, Canada
Contact:

Post by busonerd » Fri Jun 22, 2007 10:52 am

Hi,

If you can post your design name, I can tell you where its failing.

Cheers,

--David Carne

denisbest
Posts: 25
Joined: Thu Jun 21, 2007 9:38 pm
Location: Buffalo Grove, IL

Post by denisbest » Fri Jun 22, 2007 12:23 pm

David,

My design is "LED Matrix". I fixed all errors on each of the layers that ViewPlot found, but still no go.

Thanks for your help!

busonerd
Ex-SFE Guru
Posts: 700
Joined: Fri Jun 17, 2005 11:08 am
Location: Vancouver, BC, Canada
Contact:

Post by busonerd » Fri Jun 22, 2007 1:39 pm

Hi - Looking at your returned email, I see that on the top layer returned image, there are some pink colored pads indicating that the trace runs to close to them.

Fixing those should cause your design to pass! Also, the board dimensions around the edge is 0 mils, either put that in a silkscreen layer, or make it 8 mil.

Cheers,

--David Carne

denisbest
Posts: 25
Joined: Thu Jun 21, 2007 9:38 pm
Location: Buffalo Grove, IL

Post by denisbest » Fri Jun 22, 2007 9:28 pm

busonerd wrote:Hi - Looking at your returned email, I see that on the top layer returned image, there are some pink colored pads indicating that the trace runs to close to them.

Fixing those should cause your design to pass! Also, the board dimensions around the edge is 0 mils, either put that in a silkscreen layer, or make it 8 mil.

Cheers,

--David Carne
I found that dimensions layer was not added with the gerber files. I found many more errors and tried so many different things, but still nothing. Can you please comment on my latest failed test? My design is still "LED Matrix".

denisbest
Posts: 25
Joined: Thu Jun 21, 2007 9:38 pm
Location: Buffalo Grove, IL

Post by denisbest » Sun Jun 24, 2007 12:34 pm

Fixed everything but still cannot pass the bot. What should I do?

busonerd
Ex-SFE Guru
Posts: 700
Joined: Fri Jun 17, 2005 11:08 am
Location: Vancouver, BC, Canada
Contact:

Post by busonerd » Mon Jun 25, 2007 8:54 am

Just looked at your design -you still have a 0 mil border around your board.

Cheers,

--David Carne

denisbest
Posts: 25
Joined: Thu Jun 21, 2007 9:38 pm
Location: Buffalo Grove, IL

Post by denisbest » Mon Jun 25, 2007 10:03 am

Thank you thank you thank you.

Well, it took me 5 days of endless attempts to solve it and the last issue was the board edge. Thank you David, can't even describe how happy i am since it's my first design.

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