SparkFun Forums

[gimpo]

Yes, another question about polygons...

Following the instruction of the IC manufacturer, I have to create and independent ground plane for the oscillator stuff and route it directly to the ground pin of the IC itself. I thought: "it's easy! I will use polygons!", but I have encounterd a small problem.

I have created a new project from the scratch just for fun/experimenting. What follow is what I have done.

In the schematics:

1. I have joined the GND connector-pin and GND IC-pin to the same net named "GND" (by using the net tool);
2. I have joined oscillator caps GND pin to another net named "GND2" (by using the net tool);

In the PCB layout:

1. I drawn a polygon around the oscillator stuff, named it as "GND2" (with Rank = 1);
2. I drawn a polygon around all the board, named it as "GND" with (Rank = 2);

Here the result

gplane01.jpg

Next there was a problem: the inner plane is well isolated from the rest, but I need to route it to the GND-pin of the IC anyway. I thought: "how I can achieve that?"
In the schematics both planes belong to separated nets: GND and GND2. This means that if I draw a net-wire between them EAGLE will ask me to join the nets adopting one name. If I do so, in the pcb layout editor, the separated plane will be merged into one, covering the entire board. Grrrrrr!

My solution is to keep the two nets independent and manually route a new trace from the inner ground plane to the GND pin of the IC:

gplane02.jpg

By hitting the ratsnest button I've got what I want:

gplane03.jpg

Here arrive my question. By hitting the DRC button I get two overlap errors (see image in the next post): there is no way to avoid that errors?
I mean... there is no clean way to add an additional route to a pad without having EAGLE complaining about that? :think:

[gimpo]

Here the overlap errors (2 in total):

gplane04.jpg

[gimpo]

Nobody knows?

I was thinking to a poor solution:
to design a foo device composed of two pins that are connected internally. After adding this device to the schematic, the pins can be connected to the GND and GND2 nets separately. In this way EAGLE will not ask me to join both nets adopting one name.

[Ross Robotics]

Just use the ground plane to ground the oscillator circuit.

[gimpo]

Just use the ground plane to ground the oscillator circuit.

It will not work, it's mandatory to route the isolated plane to one specific pin of the IC. It has not to be merged with the PCB plane.

Obviously, the drawings above represent just a circuit made on the fly in order to post an example here.
I would have a schematic consistent with the PCB layout but seems not possible. One has to manually draw a route. But doing so, the schematic has no sense.

Look here below, the 3v3 and GND signals comes from the connector JP1, while GND3 pins seems connected to nowhere. This has no sense... :think:

gplane05.jpg

[Ross Robotics]

Just skimmed the STN1110 datasheet and I see no mention of using a different GND plane, but I could have missed it. Even the schematic in the datasheet uses the same GND. The only statement I found concerning the oscillator circuit is quoted from the datasheet below.

The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the STN1110 ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed.

I also looked at other schematics and they all have the circuit on the same GND plane. Even Sparkfun's board is on the same GND plane. But you can do you what you want.

[gimpo]

Just skimmed the STN1110 datasheet and I see no mention of using a different GND plane, but I could have missed it. Even the schematic in the datasheet uses the same GND. The only statement I found concerning the oscillator circuit...

Exactly, that ground plane is an isolated one. There is a vast literature about isolating the oscillator, is not an option. In this (unique) case I will not care if Sparkfun does it or not, I prefer to follow several hundreds of thousands of electronic engineers in the world doing so.
Furthermore, experienced engineers (and book) strongly recommend to adopt distinct ground planes for analog and digital devices too.

Anyway I don't want to generate a flame on the argument. My problem is purely concerning the use of EAGLE software to achieve a result: consistency between schematics and layout. That's all.

As I understand, this is a well know issue of EAGLE that makes almost impossible to join somehow two distinct nets when they are named differently. Drawing a net segment between them will ineluctably transform them in the same net, by definition

As I see by googling the unique solution is to design a foo component with two pins that are joined internally. After one has to use this symbol to join the two nets so EAGLE will not complain about that. Somebody call it "short" component, someone else call it "virtual short" or "Connector" :

https://www.element14.com/community/thr ... hread=true

http://electronics.stackexchange.com/qu ... c-separate

[Ross Robotics]

Just approve it in Eagle.

[gimpo]

Just approve it in Eagle.

Yes, but in this way the schematics will not be consistent with the PCB layout.

Anyway, it seems the easiest solution...

[languer]

Not sure I would call this an Eagle only issue. Most of the CAD systems I've seen used subscribe to this. Some already have a special connector element in their libraries, but the idea is the same. Layout designers actually want this so as to make sure the separate grounds are joined only at the one particular point. That way when they run the rules check everything adds up.

[gimpo]

No idea how to define the missing feature of Eagle. Is not an issue per se since the software works as it should. Maybe it's just a lack in the software features list...

I'm struggling about how to realize a connector/short/virtual-short component.
The most common approach is to design a two-pins part by using SMD pins in the package editor. The trick is to make the pads so close (less than 1 micro Inch) that EAGLE will consider the pins separated, while they will be joined when the PCB is produced.

Problems with above approach:

1. SMD pads will remain exposed to open air when the PCB is manufactured;
2. one has to modify DRC clearance rules in order to make EAGLE not complaining about the two pins.

Is still not clear to me how to overcome above problems. For example I cannot understand how modified DRC (with lower clearance) rules can be applied only at the connector component and not to the entire PCB... I've read also about tricks concerning the stop mask and other layers.

Honestly things are getting too complicated for my personal taste... I give up.
I love EAGLE but still today I think the software products should help people to solve problems, not creating new ones.

[n1ist]

The caps should return to pin 8, not to pin 19; the goal is to keep the circulating currents in a small loop.

Not sure if Eagle would allow this - can you put a cutout region in the ground plane where the crystals and cap are, and then put a pour in the cutout for the isolated region. Connect the isolated region with a fat trace to pin 8.
/mike

[gimpo]

The caps should return to pin 8, not to pin 19; the goal is to keep the circulating currents in a small loop.
/mike

Hi Mike, you made a right observation. Anyway the draw above was just an example, I tried to show the path of the trace going to the GND pin more clear/evident as possible.

Not sure if Eagle would allow this

Even if I'm using Eagle since many months I have to admit that I go in panic when I get an overlap error. I feel myself guilty, talking with a psychologist doesn't help!
My greatest fear (apart from schematics-and-layout consistency) is about the PCB manufacturer claiming about that overlaps. Do you have any experience about that? I mean... if I intentionally manually route a trace to join a pin with a pre-existing route (because I wanto to do so) then will I have problems when GERBER files are produced (even if I accepted the overlap error on Eagle)?

put a pour in the cutout for the isolated region. Connect the isolated region with a fat trace to pin 8.
/mike

I would also going further: to create a guard-ring in the top-layer and an isolated ground plane on the bottom layer (as suggested from sophisticated design engineers). Maybe that is too much? The isolated ground plane is enough in your opinion?

EDIT: maybe you mean exactly what is called a "guard-ring"?

[gimpo]

Not sure if Eagle would allow this - can you put a cutout region in the ground plane where the crystals and cap are, and then put a pour in the cutout for the isolated region. Connect the isolated region with a fat trace to pin 8.
/mike

Did you mean something like this?

cutout.jpg

But now where the GND pin of the caps should go? To the guard ring? The inner plane is attached to nowhere.

EDIT: ooops, the guard ring should surround the oscillator pins too. I've forgot of that in the drawing above.

[n1ist]

I was thinking more like this. Not sure if it makes a huge difference at lower frequencies; it may help with EMI.

osc.JPG

/mike