SparkFun Forums

[drwho9437]

I am not sure I understand the price page perhaps someone who has used them will clear it up for me.

I have a 2 layer board, 3x2 inch I would want tiled to fill up the panel. Do I just give them the 2x3 inch board and say tiled please, and then get back the boards at the base price or does it cost extra to have them cut apart?

Seems like what they are trying to say:
"The size above means total size of ONE Design combined (Price dose not apply to combine several designs together). For example if you have a 2layers 2"X2" with standard spec,USD99 include shipping to North America we will make 38pcs individual board for you, if you need panelize we will do the step and repeat free of charge."

I presume they just need the same files as BatchPCB?

[n1ist]

They will panelize for free with the $89 or $99 special. Just send Shane the Gerbers for a single board, and they will do the rest. The results may come as a v-scored panel (just bend the panel on the score lines to snap apart the individual boards) or already snapped or routed. I have received both kinds from them.
/mike

[rpcelectronics]

The results may come as a v-scored panel (just bend the panel on the score lines to snap apart the individual boards) or already snapped or routed. I have received both kinds from them.

That has been my experience also. It just depends on who processes the panels that day. I usually tell Shane to mark a design for v-score and keep in the panel for anything that I plan to batch re-flow. Sometimes I ask for the individual boards. It doesn't cost more either way, so it makes sense to request what you would like and get it that way. Shane is good about making sure that happens.

[sylvie369]

So do I understand this correctly?

I have a design that is 3.375 sq. inches. They're running a special in which you get 100 sq. inches for $89.

100/3.375 = 29.63, so I'd get 29 copies of my board on the panel, either already broken up into 29 boards or scored so that I could easily separate them.

It's a standard 2 layer board, silk on just one side, standard trace and hole sizes. I'd just send them the same zipped up Gerbers and drill file that I currently send to BatchPCB? (GTS, GTO, GTL, GBS, GBO, GBL, drill)

Turn-around roughly 1 week?

[rpcelectronics]

So do I understand this correctly?

I have a design that is 3.375 sq. inches. They're running a special in which you get 100 sq. inches for $89.

100/3.375 = 29.63, so I'd get 29 copies of my board on the panel, either already broken up into 29 boards or scored so that I could easily separate them.

It's a standard 2 layer board, silk on just one side, standard trace and hole sizes. I'd just send them the same zipped up Gerbers and drill file that I currently send to BatchPCB? (GTS, GTO, GTL, GBS, GBO, GBL, drill)

Turn-around roughly 1 week?

That's about the size of it! My only variation to you is I still send my Gerbers in the older format (call me creature of habit). Turn around is closer to 10 days.

[sylvie369]

Great. I'm going to give them a shot one of these days, then.

You're the RPC Electronics guy? I have a couple of your cables, plus an Opentracker. Love the stuff.

Paul
KC9KST

[TheDirty]

Just a note, but your boards may not fit on the panel perfectly like that. The board is fixed height/width and it's unlikely your PCB will fit exactly along both axis. When they panelize they tile the board the best they can, but there maybe waste board left over. So your calculations would be based on a perfect fit.

[sylvie369]

Okay, I was wondering about that. Still, price/turnaround makes it well worthwhile, at least for any boards that I _want_ in large numbers.

[rpcelectronics]

Just a note, but your boards may not fit on the panel perfectly like that. The board is fixed height/width and it's unlikely your PCB will fit exactly along both axis. When they panelize they tile the board the best they can, but there maybe waste board left over. So your calculations would be based on a perfect fit.

That's a good point, Mark. GP will always "round down", meaning, they will fit the design in the panel as many times as they can completely. If there is space left over, but not quite enough for a complete board, they will just cut that away as excess. They won't kick in the extra space to give you a whole additional board.

[rpcelectronics]

Great. I'm going to give them a shot one of these days, then.

Once you do it once, you will get over the fear of doing anything wrong. I know I was nervous the first time I sent a design in directly.

Ah, one thing just came to mind! Before you submit your design, make sure to create a border of your board in the silkscreen layer. This is a requirement that Shane has to make sure they route the board properly. Make sure to add that and then re-run the CAM to make sure that is included in the Gerbers.

You're the RPC Electronics guy? I have a couple of your cables, plus an Opentracker. Love the stuff.

Yep, that is me. Glad to hear the cables and OT1+ are working out for you. Thanks for your business! Are you coming to Dayton this year? We will be back again in booth 503, in what I call the "Gray Room". Basically a concrete floor.

[sylvie369]

When you say "a border of your board in the silkscreen layer", can I assume that you simply mean that I should put a rectangle around the perimeter of the board, in the tPlace layer?

(I'm assuming that "tPlace" is a standard name for that layer, and not just something that Eagle calls it).

Or should it be on the "tsilk" layer? I haven't been using that layer at all, but if that's where the border belongs, no problem.

I can't begin to tell you how excited I am to be learning this stuff about making PCBs. I ran one a couple of years ago using the Sparkfun ttl-controlled outlet project, but I didn't really have any idea what I was doing. It's really something to be able to make some devices of my own design, and have them on these beautiful boards.

Today is my birthday - maybe I'll treat myself to my first GoldPhoenix order, and make up enough of my rocket telemetry boards to give them away to the guys in my club. As I've said in a few other places, I've paid enough tuition in my life that I don't think twice about spending $100 to learn something new.

Oh, and yes, I understand that there's no guarantee that the number of boards will come out exactly to the number I'd figured above. Obviously there's nothing they can do to make that happen, and I imagine that the maximum area numbers are determined by the size of the raw materials and perhaps the machine, so they can't just add on extra area. I'd have been very surprised if they could.
-------------------
I've never been to Dayton (well, not for the convention - I've been to Wright-Patterson several times). I'm a fairly new Ham (as you can tell from my call), though my older brother W9WI has been a ham for decades and I grew up around it. I got my license a few years ago explicitly so that I could use Big Red Bee trackers in my rockets, though I've since done some HF, and APRS on 2m as well. Mostly I'm building rocketry telemetry devices using XBee radios.

[rpcelectronics]

When you say "a border of your board in the silkscreen layer", can I assume that you simply mean that I should put a rectangle around the perimeter of the board,

Correct.

in the tPlace layer?

In the tsilk (Top Silk) layer.

(I'm assuming that "tPlace" is a standard name for that layer, and not just something that Eagle calls it).

tPlace is used to show the outline of a component when placing it. The other side of that coin is, when you run a silk.ulp to create the silk layer, the tPlace layer is used to determine where those silk marks will be placed.

tDocu also shows the outline of a component (if added at time of creation) but will not cause the silk.ulp to generate silk marks for them. I use tPlace and tDocu in combination when creating a part.

For example, when creating an SMT IC, you would want to use tPlace for the body outline, but use tDocu for the legs of the IC, overlapping the pads. This way, when you run the silk.ulp, silk markings are generated for the body of the part, but not for the legs. If it did, there would be silk marks right over your pads and that would inhibit you to solder the part to the pad

[sylvie369]

Aha. Okay, I get it. Good information - thanks. I'll put a rectangle in tsilk on my board right now.

Ooops. Okay, if I do rectangle, it seems to want to fill in the entire area. Hmm. How exactly am I going to make the outline?

[rpcelectronics]

Ooops. Okay, if I do rectangle, it seems to want to fill in the entire area. Hmm. How exactly am I going to make the outline?

Use the Line Tool and change the layer in the top left drop-down box to tSilk.

[MichaelN]

Before you submit your design, make sure to create a border of your board in the silkscreen layer. This is a requirement that Shane has to make sure they route the board properly.

I've never had them require this. I use Protel, and normally put the board outline on the "Keepout" layer. I include a "Readme.txt" with the Gerbers that explicitly states what each Gerber file is for...