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Questions relating to designing PCBs
By arader
#50162
Hi all,

This is my first PCB, it's a backpack for an 8x8 led matrix. The matrix itself is pretty small, so this PCB is a lot smaller than I'd like :) I used TinyCAD and FreePCB to do the schematic and pcb. I would be eternally grateful if any of you could take a look and let me know if there are any problems.

The PCB itself is tiny, ~1.2 inches square. I tried packing it all in on a 2 layer board, but I quickly realized I'd need 4 layers. I plan on having this fabbed at BatchPCB, so keep that in mind in case you see anything that they can't do.

I've designed the layers as such:

top
+5
GND
bottom

FreePCB's DRC passed with the following rules (all units are mils):

min. trace width: 8
min pad to pad: 8
min pad to trace: 8
min trace to trace: 8
min hole to pad or trace: 15
min hole to hole: 25
min annular ring (pins): 7
min annular ring (vias): 5
min board edge to any copper: 25
min copper area to copper area: 10

will these satisfy BatchPCB's rules? I'm most concerned about clearance issues and obvious design mistakes. For example, is it a good idea to have two or more traces running parallel in different layers? Are my decoupling caps close enough? etc

And finally, the images:

Schematic:
http://i29.tinypic.com/2gvkkcg.png

Top:
Image

+5:
Image

GND:
Image

Bottom:
Image

All Layers:
Image

any advice will be greatly appreciated!
By gussy
#50169
arader wrote:will these satisfy BatchPCB's rules? I'm most concerned about clearance issues and obvious design mistakes. For example, is it a good idea to have two or more traces running parallel in different layers? Are my decoupling caps close enough? etc
I can't help you with all your questions but you should be fine for most of those DRC rules as the minimum for BatchPCB is 7mil and it looks like you have used 8mil rules.

If in doubt just submit it and see what the bot says.
User avatar
By bigglez
#50185
Greetings Andy,
arader wrote:This is my first PCB, it's a backpack for an 8x8 led matrix.
.....
any advice will be greatly appreciated!
Looks good (especially for a first attempt). To find out
if the BatchPCB Bot can accept your design just upload it.
(There's no obligation to order - even if it passes with
no errors).

The three issues I've noticed are:

(1) RST doesn't connect to any of the SPI connectors,
so how will you program the AVR?

(2) There are no mounting holes on the PCB, how does
the PCB/Display mount?

(3) If multiple modules are connected together, how do
they know which one is being addressed? (I would have
expected links, a jumper, or other binary device to
code each module. Are you customizing the AVR code for
each one?

Also, if you had a bigger AVR (more IO) the SPI MUX
chips would go away - possibly saving some PCB
crowding?

If all modules were slaved to one master (which may be
different to the others, and indeed not require the small
footprint), wouldn't you only need one SPI bus that drops
at each module? This would save some parts?

Have you considered breadboarding this design? A
four layer PCB is a big investment.

Comments Welcome!
By jasonharper
#50186
Your +5 and GND layers appear to be non-functional, due to being split into non-connected areas by the various traces you have running on them. A 4-layer board would ideally have NO traces on the inner layers.

Shouldn't the SPI connectors on opposite edges of the board be oriented the same way, so that adjacent modules can simply plug into each other?
By NleahciM
#50198
jasonharper wrote:Your +5 and GND layers appear to be non-functional, due to being split into non-connected areas by the various traces you have running on them. A 4-layer board would ideally have NO traces on the inner layers.

Shouldn't the SPI connectors on opposite edges of the board be oriented the same way, so that adjacent modules can simply plug into each other?
Yup - for example, pin 6 of J3 is floating due to this.

The layout is just in general sloppy and needs a lot of improvement. It should be pretty feasible to get most if not all of the traces out of the two power planes.
By arader
#50212
bigglez wrote:Looks good (especially for a first attempt).
Thanks!
bigglez wrote:(1) RST doesn't connect to any of the SPI connectors,
so how will you program the AVR?
I didn't want to squeeze on a 6pin connector that will only be used every once and a while, especially since I already have headers for all of the pins needed. When I program I'll just be using a wire from the RST pin to the programmer.
bigglez wrote:(2) There are no mounting holes on the PCB, how does
the PCB/Display mount?
Good point. The display will just be directly mouted to the pcb via its pins, but I haven't really thought about how I want to mount the board yet. If I can free up enough space on the corners I'll definitely be adding mounting holes.
bigglez wrote: (3) If multiple modules are connected together, how do
they know which one is being addressed? (I would have
expected links, a jumper, or other binary device to
code each module. Are you customizing the AVR code for
each one?

Also, if you had a bigger AVR (more IO) the SPI MUX
chips would go away - possibly saving some PCB
crowding?

If all modules were slaved to one master (which may be
different to the others, and indeed not require the small
footprint), wouldn't you only need one SPI bus that drops
at each module? This would save some parts?
I'm trying to create a design that uses a "decentralized" protocol, I don't want to have a central master with many slaves. If I did use 1 SPI bus I'd need some set amount of SS lines. Depending on the number of SS lines I create in the initial design, I'd be limited to the number of devices I can add. Instead if each backpack only talks to the 4 directly connected to it, I can get something that more closely relates to the internet. By making it so that each backpack only has 4 SS lines (and thus, the SS lines aren't shared by all nodes) the SPI bus can't be shared, since it would be impossible for nodes not directly connected to a "talking" node to know if the bus is in use. This also means I can have many different nodes communicating at once, something that might be important down the line.
bigglez wrote: Have you considered breadboarding this design? A
four layer PCB is a big investment.
I do plan on bread boarding some, but after seeing the PCB it seems like it would make much more sense to do a lot of it :) Also, other than being slightly more money, is there an difference in a 4 layer board?
jasonharper wrote:Your +5 and GND layers appear to be non-functional, due to being split into non-connected areas by the various traces you have running on them. A 4-layer board would ideally have NO traces on the inner layers.
Great find! so I guess my question is, with this small of an area and this many parts, is it feasible to expect no traces on the inner layers? This was my very first design, so I know it's going to suck, but it felt like it would be very hard to keep everything on 2 layers. If people here think it's doable, I'll definitely shoot for it though :)
jasonharper wrote:Shouldn't the SPI connectors on opposite edges of the board be oriented the same way, so that adjacent modules can simply plug into each other?
Yes and no :) I've arranged them this way so the pcb can be rotated and each side is exactly the same. I just need to make some special header that corrects the pins, and from there the pcbs can be connected in any fashion. If I went with a direct connection, the left/right and top/bottom would be different and I wouldn't be able to mate them if the node was rotated.

So, underlying theme so far: I should try again :) This time I'll shoot for no traces on pwr/gnd planes. Does anyone have any advice for this? I've looked at a few guides and it seems like its just "start with the longest line". How much would re-arranging the parts fix the routing issues?

thanks guys!
User avatar
By bigglez
#50216
Greetings Andy,
arader wrote: I'm trying to create a design that uses a "decentralized" protocol, I don't want to have a central master with many slaves. If I did use 1 SPI bus I'd need some set amount of SS lines. Depending on the number of SS lines I create in the initial design, I'd be limited to the number of devices I can add.
Why would the data flow in both directions? Doesn't
new data arrive and flow from module to module?

A time-division-Mux'd scheme would have one talker and many
listeners, each sync'd by a frame word or gap in transmission,
and each listens to all messages and only grabbing those with
the correct address block. As more modules are added the
message stream gets longer, but the basic timing is fixed.

Are you familiar with DMX-512 control for stage lighting?

This thread needs to go back to the projects forum, and
only PCB related discussion continue here, don't you
agree?
arader wrote:Instead if each backpack only talks to the 4 directly connected to it, I can get something that more closely relates to the internet.
The internet?
arader wrote: Great find! so I guess my question is, with this small of an area and this many parts, is it feasible to expect no traces on the inner layers? This was my very first design, so I know it's going to suck, but it felt like it would be very hard to keep everything on 2 layers. If people here think it's doable, I'll definitely shoot for it though :)
Part of the problem is that you are attempting a
complex design for your first project. Also, I'm
unfamiliar with the tools you are using, but it
looks as if there is no ERC and DRC functions,
that would catch silly (and obscurely silly) errors.
arader wrote:So, underlying theme so far: I should try again :) This time I'll shoot for no traces on pwr/gnd planes. Does anyone have any advice for this? I've looked at a few guides and it seems like its just "start with the longest line". How much would re-arranging the parts fix the routing issues?
In general a four layer board has two strikes compared
with a two layer board. (1) the inner layers can't be
probed or modded, (2) The PCB house has to do
electrical testing to ensure the inner layers are correctly
manufactured. Both add to cost and complexity.

If a traditional prototype (with hand wiring) is not
your cup of tea, consider making a two sides over-size
prototype to prove the concept. Sounds as if you'd need
four (or more) modules to work out the comms?

Once you have these working together spin the PCB
layout (adding more layers) to reach the final size.

Comments Welcome!
User avatar
By leon_heller
#50218
Four-layer PCBs are about twice as expensive as double-sided.

It would be cheaper to go for a double-sided board by using, say, 6/6 mil design rules and 0.3 mm hole vias; you should be able to squeeze everything in. Most PCB suppliers can manage those design rules.

A four-layer board with true ground and power planes in the middle would be better in terms of EMC, but you don't need to bother about it for a hobbyist project.

Leon
Last edited by leon_heller on Fri Jun 13, 2008 11:11 am, edited 1 time in total.
By arader
#50224
I've moved the design portion of the discussion into the project thread I have: viewtopic.php?p=50223#50223

If there are any more comments on the PCB however, please feel free!
By winston
#50353
Did you try to hand route the PCB, or was it done with the autorouter? I've found so far that I can hand route a board considerably better than (gEDA PCB) can autoroute it... so I hand route everything. Hand routing may get you two layers. It's not a sin to use the odd link wire, either, if it can save a layer.

It's also worth seeing if you can reduce the component count, for example, can you eliminate some of the 74 series logic by moving their jobs into a bigger AVR? According to Google, the TPIC6C595 is a shift register - could its function be done in software by an AVR instead? Using a bigger AVR to reduce the chip count by 4 would make the PCB far easier to route, and easily 2 layer. If the logic functions absolutely can't be done by the AVR for some reason, you could consider using programmable logic such as a small CPLD to provide the glue logic and reduce your chip count by 3.
User avatar
By bigglez
#50367
Greetings Winston,
winston wrote:According to Google, the TPIC6C595 is a shift register - could its function be done in software by an AVR instead? Using a bigger AVR to reduce the chip count by 4 would make the PCB far easier to route, and easily 2 layer. If the logic functions absolutely can't be done by the AVR for some reason, you could consider using programmable logic such as a small CPLD to provide the glue logic and reduce your chip count by 3.
It might help you to read Andy's original thread here.

Comments Welcome!
By arader
#50707
ok, I've been using eagle to do the routing and it's coming along nicely. I'm almost finished routing the single traces, and it looks like I've gotten them all on just 2 layers. For the power traces, is it a bad idea to add a +5V plane to one of the sides of the board? I don't think I'm going to be able to fit my power traces in with the signal traces, so it would be awesome if I could just make one side of the board GND, and the other side +5.

The only reason why I could think of this being a bad idea is either noise levels could increase, or maybe it would be easier for shorts to appear. If it is a bad idea to have a 5V plane, I'll probably just go to a 4 layer board, but at least this time the middle two layers will be completely dedicated to +5V and GND.
User avatar
By leon_heller
#50708
You should route critical tracks like ground and Vcc first, then route the signals.

Leon
User avatar
By bigglez
#50712
Greetings Andy,
arader wrote: I've been using eagle to do the routing and it's coming along nicely.
It would help to see your work, can you post your EAGLE files?
arader wrote: I'm almost finished routing the single traces, and it looks like I've gotten them all on just 2 layers. For the power traces, is it a bad idea to add a +5V plane to one of the sides of the board?
Please clarify, do you have two layers or four? A power (or ground)
plane is nothing more than a dedicated layer with solid copper (to
reduce resistance and inductance).
arader wrote:I don't think I'm going to be able to fit my power traces in with the signal traces, so it would be awesome if I could just make one side of the board GND, and the other side +5.
Why not make one of two layers a split plane for both power
and ground, and cut into it as needed for the second signal
layer?
arader wrote: The only reason why I could think of this being a bad idea is either noise levels could increase, or maybe it would be easier for shorts to appear.
The idea behind planes is to reduce noise by reducing the
inductance of the traces. Also, when two or more separate
planes exist they act as a shield and distributed capacitance
to reduce noise, not increase it. The effect is very
subtle unless you are operating at very high frequency and fast
edge clocks (i.e. above 100MHz).
arader wrote:If it is a bad idea to have a 5V plane, I'll probably just go to a 4 layer board.
There is a huge jump in cost for a four (or higher)
layer board. This is because the manufacturing process is twice
as complex and the boards can't be visually inspected (the
cost includes fixtures for electrical bare board testing). A two
layer board is very desireable!

Comments Welcome!
By arader
#50717
bigglez wrote:Greetings Andy,
Hi :)
bigglez wrote:It would help to see your work, can you post your EAGLE files?
I'm away from the computer with the files right now, so I'll do my best to explain better. I'll post the files later tonight.
bigglez wrote:Please clarify, do you have two layers or four?
Right now I have 2 layers with signal traces in both. I haven't routed the power and ground lines yet, so I'm trying to figure out the best course of action.

The way I see it, I have two options:

1) move to a 4 layer board. The pros of this are that I can have a dedicated gnd layer and a dedicated +5 layer. Connecting the power/gnd pins is as easy is adding a via to the correct layer. The cons are cost and complexity as you mentioned. I'd very much like to not need a 4 layer board :)

2) Use eagle's polygon tool to create a GND plane and a +5v plane. I could either split each of the 2 pcb layers to contain half gnd, half +5, or I could have one layer be the gnd, and the other layer be the +5. I'm concerned that it could be dangerous to have a large area of the board contain 5 volts by causing a short or something. Is this a valid concern? or is it standard design to have a +5V plane on a 2 layer board?
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