SparkFun Forums 

Where electronics enthusiasts find answers.

flashing marvell feroceon 88f5181

Open source ARM Debugger

By tselei
-  Wed Dec 19, 2007 1:25 am #39779
omissam1972 wrote:hi tselei and thanks for the aid,

I have update openocd to the 217,
but I do not succeed to stop the marvell 88f5181, in fact:
root@massimo-desktop:~# telnet 127.0.0.1 4444
Trying 127.0.0.1...
Connected to 127.0.0.1.
Escape character is '^]'.
Open On-Chip Debugger
> poll
target state: running
> halt
requesting target halt...
> poll
target state: running
> load_image uboot.bin 0xff800000 bin
458884 byte written at address 0xff800000
downloaded 458884 byte in 0s 1978us
>
qhile the log in the openocd:
root@massimo-desktop:/opt/openocd/trunk/src# openocd -f openocd.cfg
Info: openocd.c:93 main(): Open On-Chip Debugger (2007-09-05 09:00 CEST)
Error: embeddedice.c:181 embeddedice_build_reg_cache(): unknown EmbeddedICE version (comms ctrl: 0x00000018)
Info: server.c:67 add_connection(): accepted 'telnet' connection from 0
Warning: arm7_9_common.c:1937 arm7_9_write_memory(): target not halted
the file openocd.cfg:
#daemon configuration
telnet_port 4444
gdb_port 3333

#interface
interface parport
parport_port 0x378
parport_cable wiggler
#parport_cable old_amt_wiggler
jtag_speed 1
#use combined on interfaces or targets that can't set TRST/SRST separately
#reset_config trst_and_srst srst_pulls_trst
#reset_config trst_only
#reset_config trst_and_srst combined
reset_config srst_only

#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag_device 4 0x1 0xf 0xe

jtag_nsrst_delay 1200
jtag_ntrst_delay 1200

#target configuration
daemon_startup reset

#target <type> <endianness> <startup mode> <chainpos> <variant>
target arm926ejs little run_and_halt 0 arm926ejs
run_and_halt_time 0 500

# planing with flash code - work in progress
working_area 0 0x00400000 0x40000 nobackup

# driver addr size chip_width bus_width options
flash bank cfi 0xff800000 0x400000 1 2 0
It is possible to stop the chip marvell?

tanks

Hi,
Because the JTAG sequencry is not the same between ARM926 and 88F5x,
you need a patch to make the open OCD to stop 88F5x or you will not stop the CPU or not resume the CPU

Currently, I have a test version openOCD that works on 88F5x and 88F6x but it is not fully tested yet.

By omissam1972
-  Wed Feb 27, 2008 1:58 pm #43613
hi,
thanks to Nicolas Pitre for the carried out job up to now.

Now, with the new version of openocd I could restore u-boot on mine router WNR854T NETGEAR?

thanks

By davygravy
-  Mon Mar 10, 2008 6:25 pm #44472
you can certainly try....

I have met with more success with my LSProV2 now... having JTAG-unbricked it perhaps 10 times or so now within the last 2-3 weeks.

For me, the version that I have had the best luck with is svn335.

I have put my notes/HOWTO here...
JTAG and OpenOCD for the LSPro.
This is not for a router, but rather for a NAS device, but it is Feroceon based... as in 88f5182.

Your board is undoubtedly differently but maybe you can find success.

Halting continues to be the difficult part.

Good luck!

By omissam1972
-  Sun Mar 16, 2008 1:20 am #44769
hi, and thanks for the participation

my problem remains in making to recognize the flash. in fact:

Marvell>> flinfo
Bank # 1: INTEL 28F640J3A (64 Mbit)
Size: 8 MB,Bus Width: 2, device Width: 2.
Flash base: 0xff800000,Number of Sectors: 64 Type: REGULAR.
Sector Start Addresses: ....

and my config .cfg is:
# target <type> <endianess> <reset_mode>
target feroceon little reset_init 0
# flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
flash bank cfi 0xff800000 0x800000 2 2 0 jedec_probe

answer of openocd:
> halt
target was already halted
> poll
target state: halted
target halted in Thumb state due to debug request, current mode: System
cpsr: 0xffffffff pc: 0xffffffe3
MMU: disabled, D-Cache: disabled, I-Cache: disabled
> flash banks
#0: cfi at 0xff800000, size 0x00800000, buswidth 2, chipwidth 2
> flash probe 0
value captured during scan didn't pass the requested check: captured: 0x0f check_value: 0x01 check_mask: 0x0f
in_handler reported a failed check
... ... ... ...
JTAG error while reading cpsr
probing failed for flash bank '#0' at 0xff800000

where it is the error?

By davygravy
-  Sun Mar 16, 2008 10:08 am #44784
omissam, it does appear to be correctly halted. That looks good.

did you try a reset also? then a halt? I also have found that I frequently need to restart my USB-JTAG device by unplugging it, and also power down the target device completely. I see you are using a wiggler/paraport device, so you might have to restart your computer - not sure, though (I haven't flashed w/ a paraport device and am not familiar w/ them...).


are you sure your flash bank line in your config file is correct?
-are there really two banks there?
-the address 0xff800000 looks correct from the uboot-log that you posted...
- is the size of 8MB correct ? 0x800000 ?
-

Also, I use
Code: Select all
target feroceon little reset_init 0
instead... not sure if it would make a difference, but you can try...

I am not able to get "working area" to function ... so I have that turned off...

My current config is posted in the article : http://buffalo.nas-central.org/index.ph ... ng_OpenOCD

good luck to you

davy

EDIT: I have found a difference in behavior between when serial and ethernet are connected to the board vs. when *only* JTAG is connected... it seems to behave better sometimes when only JTAG is connected...

By omissam1972
-  Tue Mar 18, 2008 11:50 am #44933
thanks davygravy,
the number of chip flash present in the router are n.1 (INTEL 28F640J3A).

When u-boot it worked I was successful to conserve these data:
Code: Select all
| | | |   | __ )  ___   ___ | |_
| | | |___|  _ \ / _ \ / _ \| __|
| |_| |___| |_) | (_) | (_) | |_
 \___/    |____/ \___/ \___/ \__|  ** LOADER **
 ** MARVELL BOARD: RD-88F5181L-VOIP-GE LE

U-Boot 1.1.1 (Mar 29 2006 - 03:28:49) Marvell version: 1.7.3

DRAM CS[0] base 0x00000000   size  32MB
DRAM Total size  32MB
[8192kB@ff800000] Flash:  8 MB
Addresses 20M - 0M are saved for the U-Boot usage.
Mem malloc Initialization (20M - 16M): Done

Soc: 88F5181 B1
CPU: ARM926 (Rev 0) running @ 500Mhz
SysClock = 166Mhz , TClock = 166Mhz


USB 0: host mode
PCI 0: PCI Express Root Complex Interface
PCI 1: Conventional PCI, speed = 33000000
Net:   egiga0 [PRIME]
Hit any key to stop autoboot:  0
Marvell>>
and this:
Code: Select all
 0  
### JFFS2 loading 'uImage' to 0x400000                                      
Scanning JFFS2 FS: .. done.                           
### JFFS2 load complete: 900120 bytes loaded to 0x400000                                                        
## Booting image at 00400000 ...                                
   Image Name:   Linux-2.4.27-vrs1                                  
   Created:      2006-12-11   5:20:50 UTC                                         
   Image Type:   ARM Linux Kernel Image (uncompressed)                                                      
   Data Size:    900056 Bytes = 879 kB                                      
   Load Address: 00008000                         
   Entry Point:  00008000                         
   Verifying Checksum ... OK                            
OK  

Starting kernel ...                   

Uncompressing Linux.............................................................                                                                                
. done, booting the kernel.                           
ZLinux version 2.4.27-vrs1 (joshua@localhost.localdomain) (gcc version 3.4.4 (re                                                                                
lease) (CodeSourcery ARM 2005q3-1)) #20 Mon Dec 11 13:19:42 CST 2006                                                                    
CPU: ARM926EJ-Sid(wb) revision 0                                
Machine: MV-88fxx81                   
Using UBoot passing parameters structure                                        
Sys Clk = 166000000, Tclk = 166000000                                     


- Warning - This LSP release was tested only with U-Boot release 1.7.3                                                                      

On node 0 totalpages: 8192                          
zone(0): 8192 pages.                    
zone(1): 0 pages.                 
zone(2): 0 pages.                 
Kernel command line: console=ttyS0,115200 root=/dev/                                                  
192.168.1.101:::DB88FXX81:eth0:none                                   
gppMask = [0x130]                 
Calibrating delay loop... 331.77 BogoMIPS                                         
Memory: 32MB 0MB 0MB 0MB = 32MB total                                     
Memory: 30292KB available (1681K code, 326K data, 72K init)                                                           
Dentry cache hash table entries: 4096 (order: 3, 32768 bytes)                                                             
Inode cache hash table entries: 2048 (order: 2, 16384 bytes)                                                            
Mount cache hash table entries: 512 (order: 0, 4096 bytes)                                                          
Buffer cache hash table entries: 1024 (order: 0, 4096 bytes)                                                            
Page-cache hash table entries: 8192 (order: 3, 32768 bytes)                                                           
CPU: Testing write b                   
POSIX conformance testing by UNIFIX                                   
init hw started.                

CPU Interface             
-------------             
SDRAM_CS0 ....base 00000000, size  32MB                                       
SDRAM_CS1 ....disable                     
SDRAM_CS2 ....disable                     
SDRAM_CS3 ....disable                     
PEX0_MEM ....base e0000000, size 128MB                                      
PEX0_IO ....base f2000000, size   1MB                                     
PCI0_MEM ....base e8000000, size 128MB                                      
PCI0_IO ....base f2100000, size   1MB                                     
INTER_REGS ....base f1000000, size   1MB                                        
DEVICE_CS0 ....no such                      
DEVICE_CS1 ....no such                      
DEVICE_CS2 ....no such                      
DEV_BOOCS ....base f4000000, size  16MB                                       
PCI: bus0: Fast back to back                             
HW already initialized.                       
PCI: bus1: Fast back to back transfers enabled                                              
Linux NET4.0 for Linux 2.4                          
Based upon Swansea University Computer Society NET3.039                                                       
Initializing RT netlink socket                              
 bankwidth 2, base f4000000, size 1000000                                         

  Marvell Development Board (LSP Version 1.0.4)-- RD-88F5181L-VOIP-GE                                                                     

 Detected Tclk 166000000 and SysClk 166000000                                             
Starting kswapd               
devfs: v1.12c (20020818) Richard Gooch (rgooch@atnf.csiro.au)                                                             
devfs: boot_options: 0x1                        
JFFS2 version 2.1. (C) 2001 Red Hat, Inc., designed by Axis Communicati                                                                     
pty: 256 Unix98 ptys configured                               
Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI en                                                                                
abled     
ttyS00 at 0xf1012000 (irq = 3) is a 16550A                                          
Marvell Gigabit Ethernet Driver 'egiga':                                        
  o Ethernet descriptors in DRAM                                
  o DRAM SW cache-coherency                           
  o Loading network interface                             
  o Using switch header mode                            
qdInit      
BoardID = eqdStart: CPU port 0x3                                
----set PPU En              
Switch driver initialized                         
Can't get netConfig: Use default                                
UNM is not initialized yet                          
2 VLANs created: CpuPortMask = 0xa7                                   
vid=0:  DISABLED(0), portMask=0x750, portNum=5                                              
vid=1:       VLAN_1, portMask=0x04, portNum=1                                             
vid=2:       VLAN_2, portMask=0xa3, portNum=4                                             
vid=12: ISOLATED(12), portMask=0x00, portNum=0                                              
Port - Vlan           
 0  - VLAN_2            
 1  - VLAN_2            
 2  - VLAN_1            
 3  - VLAN_ALL              
 4  - DISABLED(0)                 
 5  - VLAN_2            
 6  - DISABLED(0)                 
 7  - VLAN_2            
load virtual interface vid = 1                              
 register if with name                      
Init the hal            
: Ilegal MTU value 1500,  rounding MTU to: 1506                                               
 if eth0 registered                   
load virtual interface vid = 2                              
 register if with name                      
 if eth1 registered                  
PPP generic driver version 2.4.2                                
physmap flash device: 1000000 at f4000000                                         
cfi_cmdset_0001: Erase suspend on write enabled                                               
Using buffer write method                         
Using physmap partition definition                                  
Creating 6 MTD partitions on "phys_mapped_flash":                                                 
0x00000000-0x00600000 : "root"                              
0x00600000-0x00620000 : "nvram"                               
0x00620000-0x00640000 : "nvram default"                                       
0x00640000-0x00660000 : "POT"                             
0x00660000-0x00680000 : "Traffic Meter"                                       
0x00700000-0x00800000 : "uboot"                               
Initializing Cryptographic API                              
NET4: Linux TCP/IP 1.0 for NET4.0                                 
NET4: Linux TCP/IP 1.0 for NET4.0                                 
IP: routing cache hash table of 512 buckets, 4Kbytes
TCP: Hash tables configured (established 2048 bind 4096)
IPv4 over IPv4 tunneling driver
GRE over IPv4 tunneling driver
Linux IP multicast router 0.06 plus PIM-SM
ip_conntrack version 2.1 (8192 buckets, 65536 max) - 348 bytes per conntrack
ip_tables: (C) 2000-2002 Netfilter core team
ipt_time loading
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
NET4: Ethernet Bridge 008 for NET4.0
Fast Floating Point Emulator V0.94M by Peter Teichmann.
cramfs: wrong magic
jffs2_scan_inode_node(): Data CRC failed on node at 0x0037bd70: Read 0x764044df,
 calculated 0x00e21be9
VFS: Mounted root (jffs2 filesystem).
Mounted devfs on /dev
Freeing init memory: 72K
8Z

BusyBox v1.1.0 (2006.12.07-07:38+0000) Built-in shell (ash)
Enter 'help' for a list of built-in commands.

/bin/sh: can't access tty; job control turned off
/ #
and this is my configuration of openocd:
Code: Select all
#daemon configuration
telnet_port 4444
gdb_port 3333

#interface
interface parport
parport_port 0x378
parport_cable wiggler
#parport_cable old_amt_wiggler
jtag_speed 1

# use combined on interfaces or targets that can't set TRST/SRST separately
reset_config srst_only
#reset_config trst_and_srst


# jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag_device 4 0x1 0xf 0xe

#jtag_nsrst_delay 500
#jtag_ntrst_delay 500

# target configuration
# target <type> <endianess> <reset_mode>
# if chain_pos is not zero it seg faults

#target arm926ejs little reset_init 0
target feroceon little reset_init 0
run_and_halt_time 0 30

#working_area 0 0xc8010000 0x400 nobackup

# flash configuration
# flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
flash bank cfi 0xff800000 0x800000 1 1 0 jedec_probe
I have tried also with:
Code: Select all
flash bank cfi 0xff800000 0x800000 1 2 0 jedec_probe
Code: Select all
flash bank cfi 0xff800000 0x800000 2 1 0 jedec_probe
the result is always equal:
Code: Select all
JTAG error while reading cpsr
probing failed for flash bank '#0' at 0xff800000

By davygravy
-  Wed Mar 19, 2008 10:22 am #44997
hi massimo,

I've looked over your output, and I can't see anything obvious wrong (maybe I missed something... ?)...

I know you've been working at this for a while... so I offer the customary encouragement.... and maybe two side-thoughts/suggestions...

1. Have you posted your question about jtag and/or flash structure of your router to a forum that is dedicated to just your brand of router? It is a Netgear, right? someone there may know something about the flash structure that you are missing...



2. Could you get information about the flash structure by looking at the mtd devices? just a thought... like here : http://buffalo.nas-central.org/index.ph ... elFlashROM

your device is very different from this one, but maybe someone who has the same Netgear router may have that information for you...

3. Another source of information about the flash structure in your router might be visible in the U-Boot source... this is Marvell UBoot 1.7.3, and this link can provide you with the same or similar source...

http://gpl.nas-central.org/D-LINK/DSMG- ... oot.tar.gz

Please note that this is not Netgear source, but rather from DLink, but the boards are structured similarly and both use the Marvell UBoot (of course each vendor will make some tweaks further).

If you look at your UBoot output that you had saved and posted, it mentions:
Code: Select all
 ** MARVELL BOARD: RD-88F5181L-VOIP-GE LE
Now of you look throught the makefile in the source, you may be able to see some details about the structure of the flash, number of banks, size, etc. The README in the source can help decode the various
#define statements... and you will see references to the Uboot stamp that I quoted you from.
This is not the easiest way, but perhaps you will find a clue...

I'm wondering if it may be stored in NAND and not in NOR. You may see evidence of that in the UBoot source, as well.


Best of luck...

davygravy

By omissam1972
-  Wed Mar 19, 2008 1:18 pm #45010
hi davygravy,
many thanks for written how much over.
I have found in the portale netgear sources of firmware with u-boot enclosed.
From the reading of files (README) from you indicated to me, I have gained the following parts:

./u-boot_88fxx81-1_7_3/include/configs/db88f5181.h
Code: Select all
/*
 * (C) Copyright 2003
 * Texas Instruments.
 * Kshitij Gupta <kshitij@ti.com>
 * Configuation settings for the TI OMAP Innovator board.
 *
 * (C) Copyright 2004
 * ARM Ltd.
 * Philippe Robin, <philippe.robin@arm.com>
 * Configuration for Integrator AP board.
 *.
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#ifndef  MV_88F5181
#define MV_88F5181
#endif
#include "/board/mv88fxx81/mvSysHwConfig.h"
/************/
/* VERSIONS */
/************/
#define CONFIG_IDENT_STRING	" Marvell version: 1.7.3"

/* version number passing when loading Kernel */
#define VER_NUM 0x01070300           /* 1.7.3 */

/********************/
/* MV DEV SUPPORTS  */
/********************/	
#define CONFIG_PCI           /* pci support               */
#undef CONFIG_PCI_1         /* sec pci interface support */

/**********************************/
/* Marvell Monitor Extension      */
/**********************************/
#define enaMonExt()( /*(!getenv("enaMonExt")) ||\*/\
		     ( getenv("enaMonExt") && \
                       ((!strcmp(getenv("enaMonExt"),"yes")) ||\
		       (!strcmp(getenv("enaMonExt"),"Yes"))) \
		     )\
		    )

/********/
/* CLKs */
/********/
#ifndef __ASSEMBLY__
extern unsigned int mvSysClkGet(void);
extern unsigned int mvTclkGet(void);
extern unsigned int mvCntmrClkFreqGet(unsigned int);
#define UBOOT_CNTR		0		/* counter to use for uboot timer */

#define CFG_HZ			mvCntmrClkFreqGet(UBOOT_CNTR)		
#define CFG_TCLK                mvTclkGet()
#define CFG_BUS_HZ              mvSysClkGet()
#define CFG_BUS_CLK             CFG_BUS_HZ
#endif

/********************/
/* Dink PT settings */
/********************/
#define CFG_MV_PT

#ifdef CFG_MV_PT
#define CFG_PT_BASE  (CFG_MALLOC_BASE - 0x80000)
#endif /* #ifdef CFG_MV_PT */


/*************************************/
/* High Level Configuration Options  */
/* (easy to change)		     */
/*************************************/
#define CONFIG_MARVELL		1
#define CONFIG_DB88FXX81    1 
#define CONFIG_DB88F5181	1	/* this is an DB88F1181	board*/
#define CONFIG_ARM926EJS	1		/* CPU */


/* commands */

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
				 CONFIG_BOOTP_BOOTFILESIZE)

#ifdef MV_USB
#define CONFIG_COMMANDS	((CONFIG_CMD_DFL \
			 | CFG_CMD_I2C \
			 | CFG_CMD_EEPROM \
			 | CFG_CMD_PCI \
			 | CFG_CMD_NET \
			 | CFG_CMD_PING \
			 | CFG_CMD_DATE \
			 | CFG_CMD_BSP ) & ~CFG_CMD_CACHE & ~CFG_CMD_EXT2)
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
						 | CFG_CMD_DHCP	\
						 | CFG_CMD_ELF	\
                         | CFG_CMD_I2C \
                         | CFG_CMD_EEPROM \
                         | CFG_CMD_PCI \
                         | CFG_CMD_NET \
                         | CFG_CMD_PING \
                         | CFG_CMD_JFFS2 \
                         | CFG_CMD_DATE \
			 | CFG_CMD_IDE | CFG_CMD_EXT2 \
                         | CFG_CMD_BSP ) & ~CFG_CMD_CACHE	\
										& ~CFG_CMD_BDI 	\
										& ~CFG_CMD_LOADB 	\
										& ~CFG_CMD_LOADS	\
										& ~CFG_CMD_IMI	\
										& ~CFG_CMD_NFS	\
										& ~CFG_CMD_ITEST	\
										& ~CFG_CMD_IMLS	\
										& ~CFG_CMD_FPGA	\
										& ~CFG_CMD_SETGETDCR	\
										& ~CFG_CMD_AUTOSCRIPT	\
										& ~CFG_CMD_CONSOLE	\
										)
						 
#endif

#ifdef MV_TINY_IMAGE
#undef CONFIG_COMMANDS
#define CONFIG_COMMANDS (CFG_CMD_PCI \
						| CFG_CMD_FLASH	\
						 | CFG_CMD_ENV	\
						 | CFG_CMD_NET	\
						 | CFG_CMD_IDE	\
						 | CFG_CMD_EXT2	\
						 | CFG_CMD_MEMORY	\
						 | CFG_CMD_BOOTD)
#endif

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define	CFG_MAXARGS	16		/* max number of command args	*/

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CFG_IDE_MAXBUS		4	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	CFG_IDE_MAXBUS * 8	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#undef CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_LBA48

/* which initialization functions to call for this board */
#define CONFIG_MISC_INIT_R	1      /* after relloc initialization*/
#undef CONFIG_DISPLAY_MEMMAP    /* at the end of the bootprocess show the memory map*/

#define CONFIG_ENV_OVERWRITE    /* allow to change env parameters */

#undef	CONFIG_WATCHDOG		/* watchdog disabled		*/

/* Cache */
#define CFG_CACHELINE_SIZE	32	


/* global definetions. */
#define	CFG_SDRAM_BASE		0x00000000


#define CFG_RESET_ADDRESS	0xffff0000
#if defined (DB_PRPMC)
#define CFG_MALLOC_BASE		(48 << 20) /* 48M */
#else
#define CFG_MALLOC_BASE		(16 << 20) /* 16M */
#endif
/*
 * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
 * To an unused memory region. The stack will remain in cache until RAM
 * is initialized 
*/
#define	CFG_MALLOC_LEN		(4 << 20)	/* (default) Reserve 4MB for malloc*/

#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */

#define CONFIG_INIT_CRITICAL		/* critical code in start.S */


/********/
/* DRAM */
/********/

#define CFG_DRAM_BANKS		4

/* this defines whether we want to use the lowest CAL or the highest CAL available,*/
/* we also check for the env parameter CASset.					  */
#define MV_MIN_CAL

#define CFG_MEMTEST_START     0x00400000
#define CFG_MEMTEST_END       0x00C00000

/********/
/* RTC  */
/********/
#if (CONFIG_COMMANDS & CFG_CMD_DATE)
#define CFG_NVRAM_SIZE  0x00 /* dummy */
#define CFG_NVRAM_BASE_ADDR DEVICE_CS1_BASE /* dummy */
#define CONFIG_RTC_DS1339 
#endif /* #if (CONFIG_COMMANDS & CFG_CMD_DATE) */

/********************/
/* Serial + parser  */
/********************/
/*
 * The following defines let you select what serial you want to use
 * for your console driver.
 */

#define CONFIG_BAUDRATE         115200   /* console baudrate = 115000    */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
#define CFG_DUART_IO		DEVICE_CS2_BASE
#define CFG_DUART_CHAN		0		/* channel to use for console */
#define CFG_INIT_CHAN1
#define CFG_INIT_CHAN2

#define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
#define CFG_LOADS_BAUD_CHANGE           /* allow baudrate changes       */

#define CFG_CONSOLE_INFO_QUIET  /* don't print In/Out/Err console assignment. */

/* parser */
/* don't chang the parser if you want to load Linux(if you cahnge it to HUSH the cmdline will
	not pass to the kernel correctlly???) */
/*#define CFG_HUSH_PARSER */
#undef CFG_HUSH_PARSER 
#define CONFIG_AUTO_COMPLETE

#define CFG_PROMPT_HUSH_PS2	"> "

#define	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT	"Marvell>> "	/* Monitor Command Prompt	*/
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */

/* temp no ethernet in ferocion */
/************/
/* ETHERNET */
/************/
/* to change the default ethernet port, use this define (options: 0, 1, 2) */
#define CONFIG_NET_MULTI

#define YUK_ETHADDR          	"00:00:00:EE:51:81"
#define ETHADDR          	"00:00:00:00:51:81"

#define CONFIG_IPADDR		10.4.50.146

#define CONFIG_SERVERIP		10.4.50.4

/***************************************/
/* LINUX BOOT and other ENV PARAMETERS */
/***************************************/
#if defined (DB_PRPMC) || defined(RD_88F5181L_FE) || defined(RD_88F5181L_GE)

#define CFG_BOOTARGS_END ":::DB88FXX81:eth0:none"
#else
#define CFG_BOOTARGS_END ":::DB88FXX81:egiga0:none"
#endif

#define CONFIG_ZERO_BOOTDELAY_CHECK

#define	CFG_LOAD_ADDR		0x00400000	/* default load address	*/

#undef	CONFIG_BOOTARGS

/* auto boot*/
#define CONFIG_BOOTDELAY	3 		/* by default no autoboot */

#if (CONFIG_BOOTDELAY >= 0)
#define CONFIG_BOOTCOMMAND      "tftpboot 0x400000 $(image_name);\
 setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
 ip=$(ipaddr):$(serverip)$(bootargs_end);  bootm 0x400000; "
                                                                                                             
#if defined(RD_88F5181L_FE) || defined(RD_88F5181L_GE)

#define CONFIG_BOOTARGS "console=ttyS0,115200 mtdparts=phys_mapped_flash:15m(root),1m@15m(uboot)ro"

#else

#define CONFIG_BOOTARGS "console=ttyS0,115200"

#endif

#define CONFIG_ROOTPATH	/mnt/ARM_FS/
#endif /* #if (CONFIG_BOOTDELAY >= 0) */

#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */

#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ 

#define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs  */
#define CONFIG_SETUP_MEMORY_TAGS        1
#define CONFIG_MARVELL_TAG              1
#define ATAG_MARVELL                    0x41000403

/********/
/* I2C  */
/********/
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_SPEED   100000		/* I2C speed default */

/* I2C addresses for the two DIMM SPD chips */
#define DIMM0_I2C_ADDR	0x56
#define DIMM1_I2C_ADDR	0x54

/* CPU I2C settings */
#define CPU_I2C  
#define I2C_CPU0_EEPROM_ADDR    0x51


/********/
/* PCI  */
/********/
#ifdef CONFIG_PCI
 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function     */
 #define CONFIG_PCI_PNP          	/* do pci plug-and-play         */

/* Pnp PCI Network cards */
#if defined (DB_PRPMC)
 #define CONFIG_SK98			/* yukon */
#elif defined (MV_TINY_IMAGE)
 /* nothing meanwhile */
#else
 
 #define CONFIG_EEPRO100		/* Support for Intel 82557/82559/82559ER chips */
#ifndef MV_USB
 #define CONFIG_SK98			/* yukon */
#endif
 #define CONFIG_DRIVER_RTL8029 

#endif

#endif /* #ifdef CONFIG_PCI */

#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
#define PCI_HOST_FORCE   1              /* configure as pci host        */
#define PCI_HOST_AUTO    2              /* detected via arbiter enable  */

/* for Yukon */
#define __mem_pci(x) x
#define __io_pci(x) x
#define __arch_getw(a)			(*(volatile unsigned short *)(a))
#define __arch_putw(v,a)		(*(volatile unsigned short *)(a) = (v))


/***********************/
/* FLASH organization  */
/***********************/
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
#define CFG_FLASH_PROTECTION    1

#define CFG_EXTRA_FLASH_DEVICE	DEVICE3	/* extra flash at device 3 */
#define CFG_EXTRA_FLASH_WIDTH	4	/* 32 bit */
#define CFG_BOOT_FLASH_WIDTH	1	/* 8 bit */

#define CFG_FLASH_ERASE_TOUT	120000/1000	/* 120000 - Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT	500	/* 500 - Timeout for Flash Write (in ms) */
#define CFG_FLASH_LOCK_TOUT	500	/* 500- Timeout for Flash Lock (in ms) */
#define CFG_FLASH_CFI		1

#define CFG_FLASH_BASE		BOOTDEV_CS_BASE

#if defined(RD_88F5182) && defined(MV_TINY_IMAGE)

#define	CFG_ENV_IS_IN_FLASH	1
#define	CFG_ENV_SIZE				0x1000	/* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE			0x1000
#define CFG_ENV_ADDR    			0xfffff000 

#define	CFG_MONITOR_LEN				(252 << 10)	/* Reserve 252 kB for Monitor */
#define CFG_MONITOR_BASE			(CFG_FLASH_BASE)
#define CFG_MONITOR_IMAGE_OFFSET	0x0	/* offset of the monitor from the 
											u-boot image */

#elif defined(RD_88F5181L_FE) || defined(RD_88F5181L_GE) || defined(RD_88F5182)

#define BOARD_LATE_INIT

#define	CFG_ENV_IS_IN_FLASH			1
#define	CFG_ENV_SIZE				0xA000	/* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE			0x20000
#define CFG_ENV_ADDR    			(CFG_FLASH_BASE + 0xF60000) 

#define	CFG_MONITOR_LEN				(448 << 10)	/* Reserve 448 kB for Monitor */
#define CFG_MONITOR_BASE			(CFG_FLASH_BASE + 0xF90000)
#define CFG_MONITOR_IMAGE_OFFSET	0x10000	/* offset of the monitor from the 
											u-boot image */

#else

#define	CFG_ENV_IS_IN_FLASH			1
#define	CFG_ENV_SIZE				0xA000	/* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE			0x10000
#define CFG_ENV_ADDR    			(CFG_FLASH_BASE) 

#define	CFG_MONITOR_LEN				(448 << 10)	/* Reserve 448 kB for Monitor */
#define CFG_MONITOR_BASE			(CFG_FLASH_BASE + 0x10000)
#define CFG_MONITOR_IMAGE_OFFSET	0x10000 /* offset of the monitor from the 
											u-boot image */

#endif


#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)

#if defined(RD_88F5181L_FE) || defined(RD_88F5181L_GE)
 /* Flash banks JFFS2 should use */
 #define CFG_JFFS2_FIRST_BANK    0
 #define CFG_JFFS2_NUM_BANKS     1
 
#else
 /* Flash banks JFFS2 should use */
 #define CFG_JFFS2_FIRST_BANK    1
 #define CFG_JFFS2_NUM_BANKS     1
 
#endif
#endif /* #if (CONFIG_COMMANDS & CFG_CMD_JFFS2) */


/*****************/
/* others        */
/*****************/
#define CFG_DFL_MV_REGS		0xd0000000 	/* boot time MV_REGS */
#define CFG_MV_REGS		INTER_REGS_BASE /* MV Registers will be mapped here */

#undef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE	(4 << 20)	/* regular stack - up to 4M (in case of exception)*/
#define CONFIG_NR_DRAM_BANKS 	4 

#endif							/* __CONFIG_H */
and in the file /u-boot_88fxx81-1_7_3/board/mv88fxx81/mvSysHwConfig.h
Code: Select all
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates

********************************************************************************
Marvell GPL License Option

If you received this File from Marvell, you may opt to use, redistribute and/or 
modify this File in accordance with the terms and conditions of the General 
Public License Version 2, June 1991 (the "GPL License"), a copy of which is 
available along with the File in the license.txt file or by writing to the Free 
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or 
on the worldwide web at http://www.gnu.org/licenses/gpl.txt. 

THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED 
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY 
DISCLAIMED.  The GPL License provides additional details about this warranty 
disclaimer.

*******************************************************************************/
/*******************************************************************************
* mvSysHwCfg.h - Marvell system HW configuration file
*
* DESCRIPTION:
*       None.
*
* DEPENDENCIES:
*       None.
*
*******************************************************************************/

#ifndef __INCmvSysHwConfigh
#define __INCmvSysHwConfigh


#define MV_CACHEABLE(address) ((address) | 0x80000000)

/* includes */
#define _1K         0x00000400
#define _4K         0x00001000
#define _8K         0x00002000
#define _16K        0x00004000
#define _32K        0x00008000
#define _64K        0x00010000
#define _128K       0x00020000
#define _256K       0x00040000
#define _512K       0x00080000

#define _1M         0x00100000
#define _2M         0x00200000
#define _4M         0x00400000
#define _8M         0x00800000
#define _16M        0x01000000
#define _32M        0x02000000
#define _64M        0x04000000
#define _128M       0x08000000
#define _256M       0x10000000
#define _512M       0x20000000

#define _1G         0x40000000
#define _2G         0x80000000

/* 
 *  System memory mapping 
 */


/* SDRAM: actual mapping is auto detected */
#define SDRAM_CS0_BASE  0x00000000
#define SDRAM_CS0_SIZE  _256M

#define SDRAM_CS1_BASE  0x10000000
#define SDRAM_CS1_SIZE  _256M

#define SDRAM_CS2_BASE  0x20000000
#define SDRAM_CS2_SIZE  _256M

#define SDRAM_CS3_BASE  0x30000000
#define SDRAM_CS3_SIZE  _256M

/* PEX */
#define PEX0_MEM_BASE 0x90000000
#define PEX0_MEM_SIZE _128M

#define PEX0_IO_BASE 0xf0000000
#define PEX0_IO_SIZE _1M

/* PEX Work arround */
/* the target we will use for the workarround */
#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM
/*a flag that indicates if we are going to use the 
size and base of the target we using for the workarround
window */
#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1
/* if the above flag is 0 then the following values
will be used for the workarround window base and size,
otherwise the following defines will be ignored */
#define PEX_CONFIG_RW_WA_BASE 0x50000000
#define PEX_CONFIG_RW_WA_SIZE _16M


#if defined(MV_88F1181)                              

#define PEX1_MEM_BASE 0x98000000
#define PEX1_MEM_SIZE _128M

#define PEX1_IO_BASE 0xf0100000
#define PEX1_IO_SIZE _1M

#elif defined (MV_88F5181)                           
/* PCI0: IO and memory space */
#define PCI0_MEM_BASE  0x98000000
#define PCI0_MEM_SIZE  _128M

#define PCI0_IO_BASE    0xf0100000
#define PCI0_IO_SIZE    _1M

#else                                                
#   error "CHIP not selected"                        
#endif                                               

#if defined(MV_88F5181)                              
/* Device: CS0 - SRAM, CS1 - RTC, CS2 - UART, CS3 - large flash */
#define DEVICE_CS0_BASE 0xfa000000
#define DEVICE_CS0_SIZE _2M

#define DEVICE_CS1_BASE 0xf8000000

#define DEVICE_CS1_SIZE _32M

#define DEVICE_CS2_BASE 0xfa800000
#define DEVICE_CS2_SIZE _1M

#elif defined (MV_88F1181)                           

#define FLASH_CS_BASE 0xf8000000
#define FLASH_CS_SIZE _16M


#else                                                
#   error "CHIP not selected"                        
#endif                                               

/* Internal registers: size is defined in Controllerenvironment */
#define INTER_REGS_BASE	0xF1000000


#if defined(RD_88F5182) && defined(MV_TINY_IMAGE)

#define BOOTDEV_CS_BASE	0xFFFC0000
#define BOOTDEV_CS_SIZE _256K

#elif defined(RD_88F5181L_FE) || defined(RD_88F5181L_GE) || defined(RD_88F5182)

#define BOOTDEV_CS_BASE	0xFF000000
#define BOOTDEV_CS_SIZE _16M

#else

#define BOOTDEV_CS_BASE	0xff800000
#define BOOTDEV_CS_SIZE _8M

#endif

#if defined(MV_88F5182) || defined (MV_88F5181L)

#define CRYPT_ENG_BASE	0xFB000000
#define CRYPT_ENG_SIZE	_64K

#endif


/* DRAM detection stuff */
#define MV_DRAM_AUTO_SIZE

/* These addresses defines the place where global parameters will be placed	*/
/* in case running from ROM. We Use SYS_MEM_TOP. See bootInit.c file		*/
#define DRAM_DETECT_FLAG_ADDR 	0x03000000
#define DRAM_CONFIG_ROM_ADDR 	0x03000004

/* We use the following registers to store DRAM interface pre configuration   */
/* auto-detection results													  */
/* IMPORTANT: We are using mask register for that purpose. Before writing     */
/* to units mask register, make sure main maks register is set to disable     */
/* all interrupts.                                                            */
#define DRAM_BUF_REG0	0x1011c	/* sdram bank 0 size	        */  
#define DRAM_BUF_REG1	0x20318	/* sdram config			        */
#define DRAM_BUF_REG2   0x20114	/* sdram mode 			        */
#define DRAM_BUF_REG3	0x20320	/* dunit control low 	        */          
#define DRAM_BUF_REG4	0x20404	/* sdram address control        */
#define DRAM_BUF_REG5	0x2040c	/* sdram timing control low     */
#define DRAM_BUF_REG6	0x40108	/* sdram timing control high    */
#define DRAM_BUF_REG7	0x40114	/* sdram ODT control low        */
#define DRAM_BUF_REG8	0x41910	/* sdram ODT control high       */
#define DRAM_BUF_REG9	0x41a08	/* sdram Dunit ODT control      */
#define DRAM_BUF_REG10	0x41a30	/* sdram Extended Mode		    */

/* Following the pre-configuration registers default values restored after    */
/* auto-detection is done                                                     */
#define DRAM_BUF_REG0_DV    0           /* GPIO Interrupt Level Mask Reg      */
#define DRAM_BUF_REG1_DV	0           /* ARM Timer 1 reload register        */
#define DRAM_BUF_REG2_DV    0           /* AHB to MBUS Bridge int Mask Reg    */
#define DRAM_BUF_REG3_DV	0           /* ARM Watchdog Timer Register        */
#define DRAM_BUF_REG4_DV	0           /* Host to ARM Doorbel Mask Register  */
#define DRAM_BUF_REG5_DV	0           /* ARM To Host Doorbel Mask Register  */
#define DRAM_BUF_REG6_DV	0           /* PCI Exp Uncorrectable Err Mask Reg */
#define DRAM_BUF_REG7_DV	0           /* PCI Exp Correctable Err Mask Reg   */
#define DRAM_BUF_REG8_DV	0           /* PCI Express interrupt Mask Reg     */
#define DRAM_BUF_REG9_DV	0           /* PCI Express Spare Register         */
#define DRAM_BUF_REG10_DV	0x012C0004  /* PCI Exp Acknowledge Timers (x4) Reg*/
 

#if defined (MV_88F5181)                         

/* Pex\PCI stuff */
#define PEX0_HOST_BUS_NUM		0
#define PEX0_HOST_DEV_NUM		0

#define PCI0_HOST_BUS_NUM		1
#define PCI0_HOST_DEV_NUM		0

/* no pci1 in MV_88F5181 */
#define PCI1_HOST_BUS_NUM		0
#define PCI1_HOST_DEV_NUM		0
/* no pex1 in MV_88F5181 */
#define PEX1_HOST_BUS_NUM		0
#define PEX1_HOST_DEV_NUM		0

#define PCI_ARBITER_CTRL    /* Use/unuse the Marvell integrated PCI arbiter	*/
#undef	PCI_ARBITER_BOARD	/* Use/unuse the PCI arbiter on board			*/

/* Check macro validity */
#if defined(PCI_ARBITER_CTRL) && defined (PCI_ARBITER_BOARD)
	#error "Please select either integrated PCI arbiter or board arbiter"
#endif




#elif defined (MV_88F1181)                           
/* Pex\PCI stuff */
#define PEX0_HOST_BUS_NUM		0
#define PEX0_HOST_DEV_NUM		0
/* we have a bridge */
#define PEX1_HOST_BUS_NUM		2
#define PEX1_HOST_DEV_NUM		0

/* no pci in MV_88F5181 */
#define PCI0_HOST_BUS_NUM		0
#define PCI0_HOST_DEV_NUM		0
#define PCI1_HOST_BUS_NUM		0
#define PCI1_HOST_DEV_NUM		0

#else                                                
#   error "CHIP not selected"                        
#endif                                               


/* Board clock detection */
#define TCLK_AUTO_DETECT    /* Use Tclk auto detection 		*/
#define SYSCLK_AUTO_DETECT	/* Use SysClk auto detection 	*/
#define PCLCK_AUTO_DETECT  /* Use PClk auto detection */


/* Memory uncached, HW or SW cache coherency is not needed */
#define MV_UNCACHED             0   
/* Memory cached, HW cache coherency supported in WriteThrough mode */
#define MV_CACHE_COHER_HW_WT    1
/* Memory cached, HW cache coherency supported in WriteBack mode */
#define MV_CACHE_COHER_HW_WB    2
/* Memory cached, No HW cache coherency, Cache coherency must be in SW */
#define MV_CACHE_COHER_SW       3


#if defined(MV_88F5181)                   
/************* Ethernet driver configuration ********************/

/*#define ETH_JUMBO_SUPPORT*/
/* HW cache coherency configuration */
#define DMA_RAM_COHER	    NO_COHERENCY
#define ETHER_DRAM_COHER    MV_UNCACHED 
#define INTEG_SRAM_COHER    MV_UNCACHED  /* Where integrated SRAM available */

#define ETH_DESCR_IN_SDRAM
#undef  ETH_DESCR_IN_SRAM

#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB)
#   define ETH_SDRAM_CONFIG_STR      "MV_CACHE_COHER_HW_WB"
#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT)
#   define ETH_SDRAM_CONFIG_STR      "MV_CACHE_COHER_HW_WT"
#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW)
#   define ETH_SDRAM_CONFIG_STR      "MV_CACHE_COHER_SW"
#elif (ETHER_DRAM_COHER == MV_UNCACHED)
#   define ETH_SDRAM_CONFIG_STR      "MV_UNCACHED"
#else
#   error "Unexpected ETHER_DRAM_COHER value"
 
#endif /* ETHER_DRAM_COHER */


/*********** Idma default configuration ***********/
#define UBOOT_CNTRL_DMA_DV     (ICCLR_DST_BURST_LIM_8BYTE | \
				ICCLR_SRC_INC | \
				ICCLR_DST_INC | \
				ICCLR_SRC_BURST_LIM_8BYTE | \
				ICCLR_NON_CHAIN_MODE | \
				ICCLR_BLOCK_MODE )
			   
#elif defined (MV_88F1181)                           


#else                                                
#   error "CHIP not selected"                        
#endif                                               
			   
#endif /* __INCmvSysHwConfigh */
task that the lines that interest are:
Code: Select all
#else

#define BOOTDEV_CS_BASE   0xff800000
#define BOOTDEV_CS_SIZE _8M

#endif
and:
Code: Select all
#define	CFG_ENV_IS_IN_FLASH			1
#define	CFG_ENV_SIZE				0xA000	/* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE			0x10000
#define CFG_ENV_ADDR    			(CFG_FLASH_BASE)
now:
# flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
driver -----------> cfi
base ------------> 0xFF800000
size -------------> 0xA000
chip_width -----> 1
bus_width ------> 1
driver_options -> jedec_probe

that is:
flash bank cfi 0xff800000 0xA000 1 1 jedec_probe

that of tasks?

By davygravy
-  Wed Mar 19, 2008 2:44 pm #45019
good find!

I have no idea if the values you found are correct or not... but...

I was thinking also that someone at OpenWRT may have experienced this as well...

http://wiki.openwrt.org/OpenWrtDocs/Har ... ear/WNR854

is listed and maybe in the forums there someone either knows how to do this, or may have yet another idea on flash structure...

http://forum.openwrt.org/

such as ...

http://forum.openwrt.org/viewtopic.php?id=12358


EDIT:
Sorry omissam, I now see that you already posted in OpenWRT...

Have you tried those three options with the jedec_probe option left off, since the changes by Pitre to OpenOCD?
 Return to “OpenOCD”