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Open source ARM Debugger
By fatalfeel
#194145
cortex-a7 cortex-a8 cortex-a9
their BVR offset is 0x100
their BCR offset is 0x140

/***************************************************/
but now cortex-a53
BVR offset is 0x400
BCR offset is 0x408

Debug Watchpoint Value Registe
WVR 0x800
WCR 0x808

a53 BVR
http://infocenter.arm.com/help/index.js ... IJBFF.html

a53 BVR offset
http://infocenter.arm.com/help/index.js ... JHJGC.html
http://infocenter.arm.com/help/index.js ... IJBFF.html

how to do this
change define on /root/openocd-0.10.0/src/target/armv7a.h ????

or any good way to switch support?

//0.10.0 source cortex_a.c
if (breakpoint->type == BKPT_HARD) {
while (brp_list[brp_i].used && (brp_i < cortex_a->brp_num))
brp_i++;
if (brp_i >= cortex_a->brp_num) {
LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
breakpoint->set = brp_i + 1;
if (breakpoint->length == 2)
byte_addr_select = (3 << (breakpoint->address & 0x02));
control = ((matchmode & 0x7) << 20)
| (byte_addr_select << 5)
| (3 << 1) | 1;
brp_list[brp_i].used = 1;
brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
brp_list[brp_i].control = control;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
brp_list[brp_i].control,
brp_list[brp_i].value);
}
By Valen
#194277
I think nobody understands what you want or need help for. All of what you have written reads as stating facts. What is the problem?

(Not that I will be answering, as I have no idea about OpenOCD or arm chips. I just helping you out understanding why nobody replies.
By fatalfeel
#194683
BVR BCR are useful in breakpoint on Arm cortex

CoreSight Debug Access Port address + BCR offest address can set hardware breakpoint

coretx a8 a9 a7 BCR offset are the same

but a53 is different ... how do I use openocd to debug A53

cortex_a.c need to modify so need help
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