Problem programming STM32F746 with additional memory section

Open source ARM Debugger

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Problem programming STM32F746 with additional memory section

Postby david.harrison » Fri Mar 24, 2017 11:08 am

Hi, I am using OpenOCD from within VisualGDB to program an STM32F746NG chip through the ST-LINK v2.1 programmer/debugger on-board the STM32F746 Discovery board.

The chip does program but VisualGDB throws up an error message about 1 or more unmatched memory sections.

A portion of the GDB log shows this:

~"Loading section .dtcm1, size 0x8a08 lma 0x20000000\n"
~"Loading section .isr_vector, size 0x1c8 lma 0x8000000\n"
~"Loading section .text, size 0x28910 lma 0x8000200\n"
~"Loading section .exidx, size 0x8 lma 0x8028b10\n"
~"Loading section .init_array, size 0x4 lma 0x8028b18\n"
~"Loading section .fini_array, size 0x4 lma 0x8028b1c\n"
~"Loading section .data, size 0x344 lma 0x8028b20\n"
~"Start address 0x801fdf0, load size 202804\n"
~"Transfer rate: 35 KB/sec, 9657 bytes/write.\n"
~"Section .dtcm1, range 0x20000000 -- 0x20008a08: MIS-MATCHED!\n"
~"Section .isr_vector, range 0x8000000 -- 0x80001c8: matched.\n"
~"Section .text, range 0x8000200 -- 0x8028b10: matched.\n"
~"Section .exidx, range 0x8028b10 -- 0x8028b18: matched.\n"
~"Section .init_array, range 0x8028b18 -- 0x8028b1c: matched.\n"
~"Section .fini_array, range 0x8028b1c -- 0x8028b20: matched.\n"
~"Section .data, range 0x8028b20 -- 0x8028e64: matched.\n"
&"warning: One or more sections of the target image does not match\nthe loaded file\n"

The .dtcm1 memory section IS NOT in fact mis-matched, it works perfectly well and has been programmed correctly.
The VisualGDB people tell me this is an OPENOCD beg in the way it does the memory section compare.
Whilst this does not stop my chip from being programmed, it does throw up this error message every time which is very annoying, to say the least.

Does anyone know why it does this and can this be fixed?
Posts: 1
Joined: Fri Mar 24, 2017 10:47 am

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