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Open source ARM Debugger
By jonver
#191907
Hi everybody!

I'm trying to program the ATSAM4SA16C with openOCD. I've used the following configuration file:
Code: Select all
source [find interface/cmsis-dap.cfg]

# chip name
set CHIPNAME ATSAM4SA16C

source [find target/at91sam4XXX.cfg]
set _FLASHNAME $_CHIPNAME.flash0
flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME info
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME at91sam4 0x00480000 0 1 1 $_TARGETNAME info

adapter_khz 250

init
targets
reset halt
program file.elf verify reset
exit
which fails with the error
Error: Flash controller(1) is not ready, attempting reset
Error: flash controller(1) is not ready! Error
It seems to be a problem with my second flash bank.

I'm using the same config file, but now with the following commands (to narrow down on the problem):
Code: Select all
flash info 0
Open On-Chip Debugger 0.9.0 (2015-09-02-10:42)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'swd'
adapter speed: 500 kHz
adapter_nsrst_delay: 100
cortex_m reset_config sysresetreq
adapter speed: 250 kHz
Info : CMSIS-DAP: SWD Supported
Info : CMSIS-DAP: JTAG Supported
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : CMSIS-DAP: FW Version = 01.21.0076
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 1 TDO = 0 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : clock speed 250 kHz
Info : SWD IDCODE 0x2ba01477
Info : ATSAM4SA16C.cpu: hardware has 6 breakpoints, 4 watchpoints
TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
0* ATSAM4SA16C.cpu cortex_m little ATSAM4SA16C.cpu halted
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x00401b70 msp: 0x2001a4b0
#0 : at91sam4 at 0x00400000, size 0x00080000, buswidth 1, chipwidth 1
# 0: 0x00000000 (0x2000 8kB) not protected
# 1: 0x00002000 (0x2000 8kB) not protected
# 2: 0x00004000 (0x2000 8kB) not protected
# 3: 0x00006000 (0x2000 8kB) not protected
# 4: 0x00008000 (0x2000 8kB) not protected
...
# 60: 0x00078000 (0x2000 8kB) not protected
# 61: 0x0007a000 (0x2000 8kB) not protected
# 62: 0x0007c000 (0x2000 8kB) not protected
# 63: 0x0007e000 (0x2000 8kB) not protected
Which is OK, but the following is not OK:
Code: Select all
flash info 1
Open On-Chip Debugger 0.9.0 (2015-09-02-10:42)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'swd'
adapter speed: 500 kHz
adapter_nsrst_delay: 100
cortex_m reset_config sysresetreq
adapter speed: 250 kHz
Info : CMSIS-DAP: SWD Supported
Info : CMSIS-DAP: JTAG Supported
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : CMSIS-DAP: FW Version = 01.21.0076
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 1 TDO = 0 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : clock speed 250 kHz
Info : SWD IDCODE 0x2ba01477
Info : ATSAM4SA16C.cpu: hardware has 6 breakpoints, 4 watchpoints
TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
0* ATSAM4SA16C.cpu cortex_m little ATSAM4SA16C.cpu halted
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x00401b70 msp: 0x2001a4b0
Error: Flash controller(1) is not ready, attempting reset
Error: flash controller(1) is not ready! Error

Error: auto_probe failed
I've checked the datasheet of the chip, which tells me indeed 2 flash banks exist on address 0x400000 and 0x480000. I've also checked the control addresses of these chips in the OpenOCD source, which are also correct (0x400E0A00 and 0x400E0C00)

The result of the last command, executed with "-d3" is found here:
http://pastebin.com/LmDGWLjU/

(short version:)
Debug: 1043 383 target.c:2179 target_read_u32(): address: 0x400e0c08, value: 0x00000000
Debug: 1044 383 at91sam4.c:732 EFC_GetStatus(): Status: 0x00000000 (lockerror: 0, cmderror: 0, ready: 0)
Error: 1045 383 at91sam4.c:824 EFC_StartCommand(): Flash controller(1) is not ready, attempting reset
Debug: 1046 383 at91sam4.c:835 EFC_StartCommand(): Command: 0x5a00000f
Debug: 1047 383 target.c:2267 target_write_u32(): address: 0x400e0c04, value: 0x5a00000f
Debug: 1048 383 cmsis_dap_usb.c:522 cmsis_dap_swd_run_queue(): Executing 2 queued transactions
Debug: 1049 383 cmsis_dap_usb.c:545 cmsis_dap_swd_run_queue(): AP write reg 4 400e0c04
Debug: 1050 383 cmsis_dap_usb.c:545 cmsis_dap_swd_run_queue(): AP write reg c 5a00000f
Debug: 1051 385 cmsis_dap_usb.c:522 cmsis_dap_swd_run_queue(): Executing 3 queued transactions
Debug: 1052 385 cmsis_dap_usb.c:545 cmsis_dap_swd_run_queue(): AP write reg 4 400e0c08
Debug: 1053 385 cmsis_dap_usb.c:545 cmsis_dap_swd_run_queue(): AP read reg c 0
Debug: 1054 385 cmsis_dap_usb.c:545 cmsis_dap_swd_run_queue(): DP read reg c 0
Debug: 1055 386 cmsis_dap_usb.c:600 cmsis_dap_swd_run_queue(): Read result: 0
Debug: 1056 386 cmsis_dap_usb.c:600 cmsis_dap_swd_run_queue(): Read result: 0
Debug: 1057 386 target.c:2179 target_read_u32(): address: 0x400e0c08, value: 0x00000000
Debug: 1058 386 at91sam4.c:732 EFC_GetStatus(): Status: 0x00000000 (lockerror: 0, cmderror: 0, ready: 0)
Error: 1059 386 at91sam4.c:819 EFC_StartCommand(): flash controller(1) is not ready! Error
Debug: 1060 386 at91sam4.c:1108 FLASHD_GetLockBits(): End: -4
Debug: 1061 386 at91sam4.c:1728 sam4_protect_check(): Failed: -4
Error: 1062 386 core.c:217 get_flash_bank_by_num(): auto_probe failed
Debug: 1063 386 command.c:628 run_command(): Command failed with error code -4

Any ideas?
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