- Fri Aug 14, 2015 4:17 pm
#184048
I have been using my own openocd file to connect to SAMA5D3 EK board.
Based on some examples (I managed to get my other sam9x25 board working to read and write to NAND flash as an alternative to SAM-BA!) I have been trying to get the same working for this sama5d35 board with the following code. Is there an equivalent of at91sam9 driver in the code below for at91sama5d3 family?
Based on some examples (I managed to get my other sam9x25 board working to read and write to NAND flash as an alternative to SAM-BA!) I have been trying to get the same working for this sama5d35 board with the following code. Is there an equivalent of at91sam9 driver in the code below for at91sama5d3 family?
Code: Select all
The rest of the config file snippet is as follows# Based on http://www.atmel.com/Images/doc11131.pdf (for sam9x25), The memory map in sam9x25 shows PMECC while sama5d3 shows HMSC
nand device nandflash_cs3 at91sam9 $_TARGETNAME 0x60000000 0xffffc000
at91sam9 cle 0 22
at91sam9 ale 0 21
##at91sam9 rdy_busy 0 0xfffffa00 xx
#at91sam9 ce 0 0xfffffa00 4
Code: Select all
# ARM Cortex-A5 CPU
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME sama5d3
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x4BA00477
}
if { [info exists FLASHTYPE] } {
set _FLASHTYPE $FLASHTYPE
} else {
set _FLASHTYPE nandflash_cs3
}
reset_config trst_and_srst
#Initial Adapter speed
adapter_khz 1000
# jtag scan chain
# Add new test access port
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID -ignore-version
#set CPU target name
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -endian $_ENDIAN -chain-position $_TARGETNAME -coreid 0 -dbgbase 0x80010000
# Internal SRAM work area (typically equivalent L1,L2,L3 caches in x86)
# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.
# The SAMA5D3 has two SRAM areas, one starting at 0x00300000 and the other starting at 0x00310000.
# Both areas are 64 kB long.
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x003000000 -work-area-size 0x200000 -work-area-backup 1
# blah blah here
$_TARGETNAME configure -event "reset-init" {
adapter_khz 8
echo "... Executing procedure sama5d3ek_board_initialize ...."
sama5d3ek_board_initialize
}
############################ DEFINE FLASH/RAM PARAMETERS#######################
proc sama5d3ek_board_initialize { } {
halt
echo "... acs6000 init routine ..."
# Based on Reference: http://download.ronetix.info/peedi/cfg_examples/arm9/sam9-cm.cfg
#this is the board init configuration file
#which sets up the sdram and flash memory
#so that user can download code into sdram
#and run it.
#This file is used to enabe the demo board
#when there is no code resides in the flash
#memory
#10 milliseconds
sleep 10
#3KHz JTAG Speed
adapter_khz 25
#10 milliseconds
sleep 10
# RSTC_MR : enable user reset.
mww 0xFFFFFD08 0xa5000501
# Allow user reset
mww 0xFFFFFE08 0xA5000001
# Disable watchdog
mww 0xFFFFFE44 0x3FFFAFFF
# enable all preripherals
# PMC_SCER
mww 0xFFFFFC00 0xFFFFFFFF
# PMC_PCER0
mww 0xFFFFFC10 0xFFFFFFFF
# PMC_PCER1
mww 0xFFFFFD00 0xFFFFFFFF
# enable NAND controller
mww 0xFFFFC010 0xFFFFFFFF
mww 0xFFFFFD0C 0x10001005
mww 0xFFFFC004 0x00000001
mww 0xFFFFC63C 0x02030203
mww 0xFFFFC640 0x09060906
mww 0xFFFFC644 0x00120012
mww 0xFFFFC648 0x88050585
mww 0xFFFFC64C 0x00000003
mww 0xFFFFC000 0x007f2000
mww 0xFFFFC018 0x00000000
mww 0xFFFFC084 0x00000001
mww 0xFFFFC084 0x00000010
mww 0xFFFFC070 0x00100000
# Switch to external crystal oscillator
mww 0xfffffc30 0x00001121
while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }
#sleep 100
#echo Perform PLLA initialization!
mww 0xFFFFFC80 0x00000000
# Fcpu=530MHz, Fddr=133MHz
mww 0xfffffc28 0x215C3F01
while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }
#sleep 100
mww 0xfffffc30 0x00001201
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
#sleep 100
mww 0xfffffc30 0x00001202
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
#sleep 100
echo "PLLA Done!"
#Adaptive JTAG Speed
adapter_khz 1000
echo "Perform DDR2 initialization!"
# enable ddr2 clock
#Enabling peripheral clock for MPDDR
mww 0xfffffD00 0x00020000
#enabling system clock
mww 0xFFFFFC00 0x00000004
# Init the special register for sama5d3x. MPDDRC DLL Slave Offset Register - DDR2 configuration
mww 0xFFFFEA78 0x01010001
# MPDDRC DLL Master Offset Register
mww 0xFFFFEA74 0xC5011F07
# MPDDRC I/O Calibration Register
# DDR2 RZQ = 50 Ohm
# TZQIO = 4
mww 0xFFFFEA34 0x00000404
# Step 1: Program the memory device type into the Memory Device Register
mww 0xFFFFEA20 0x00000006
# Step 2: Program the feature of DDR2-SDRAM device into the Timing Register, and into the Configuration Register
mww 0xFFFFEA08 0x00F2003D
#TPR0
mww 0xFFFFEA0C 0x22228226
#TPR1
mww 0xFFFFEA10 0x02C81C1A
#TPR2
mww 0xFFFFEA14 0x00072278
# Step 3: An NOP command is issued to the DDR2-SDRAM
mww 0xFFFFEA00 0x00000001
mww 0x20000000 0x00000000
sleep 5
# Step 4: An NOP command is issued to the DDR2-SDRAM
mww 0xFFFFEA00 0x00000001
mww 0x20000000 0x00000000
sleep 5
# Step 5: An all banks precharge command is issued to the DDR2-SDRAM.
mww 0xFFFFEA00 0x00000002
mww 0x20000000 0x00000000
sleep 5
# Step 6: An Extended Mode Register set(EMRS2) cycle is issued to chose between commercial or high
# temperature operations.
mww 0xFFFFEA00 0x00000005
mww 0x20002000 0x00000000
sleep 5
# Step 7: An Extended Mode Register set(EMRS3) cycle is issued
# to set the Extended Mode Register to "0".
mww 0xFFFFEA00 0x00000005
mww 0x20003000 0x00000000
sleep 5
# Step 8: An Extened Mode Register set(EMRS1) cycle is issued to enable DLL,
# and to program D.I.C(Output Driver Impedance Control)
# Perform a write access to DDR2-SDRAM to acknowledge this command.
# The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.
mww 0xFFFFEA00 0x00000005
# base_address | (1<<12)
mww 0x20001000 0x00000000
sleep 5
# Step 9: Program DLL field into the Configuration Register to high(Enable DLL reset)
set CR [expr [read_register 0xFFFFEA08] | 0x00000080]
mww 0xFFFFEA08 $CR
# Step 10: A Mode Register set(MRS) cycle is issied to reset DLL.
# Perform a write access to DDR2-SDRAM to acknowledge this command.
# The write address must be chosen so that BA[1:0] bits are set to 0.
mww 0xFFFFEA00 0x00000003
mww 0x20000000 0x00000000
sleep 5
# Step 11: An all banks precharge command is issued to the DDR2-SDRAM.
mww 0xFFFFEA00 0x00000002
mww 0x20000000 0x00000000
sleep 5
# Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register
mww 0xFFFFEA00 0x00000004
mww 0x20000000 0x00000000
sleep 5
# Set 2nd CBR
mww 0xFFFFEA00 0x00000004
mww 0x20000000 0x00000000
sleep 5
# Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset).
set CR [expr [read_register 0xFFFFEA08] & 0xFFFFFF7F]
mww 0xFFFFEA08 $CR
# Step 14:
mww 0xFFFFEA00 0x00000003
mww 0x20000000 0x00000000
sleep 5
# Step 15: Program OCD field into the Configuration Register to high (OCD calibration default).
set CR [expr [read_register 0xFFFFEA08] | 0x00007000]
mww 0xFFFFEA08 $CR
sleep 5
# Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value.
# Perform a write access to DDR2-SDRAM to acknowledge this command.
# The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.
mww 0xFFFFEA00 0x00000005
# base_address | (1<<12)
mww 0x20001000 0x00000000
sleep 5
# Step 17: Program OCD field into the Configuration Register
# to low (OCD calibration mode exit).
set CR [expr [read_register 0xFFFFEA08] & 0xFFFF8FFF]
mww 0xFFFFEA08 $CR
sleep 5
# Step 18: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value.
# Perform a write access to DDR2-SDRAM to acknowledge this command.
# The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.
mww 0xFFFFEA00 0x00000005
# base_address | (1<<12)
mww 0x20001000 0x00000000
sleep 5
# Step 19: A Nornal mode command is provided.
mww 0xFFFFEA00 0x00000000
mww 0x20000000 0x00000000
# Step 20: Perform a write access to any DDR2-SDRAM address
mww 0x20000000 0x00000000
# Step 21: Write the refresh rate into the count field in the Refresh Timer register.
mww 0xFFFFEA04 0x00000411
# Identify NandFlash bank 0.
nand probe nandflash_cs3
#halt
halt
# 10 milliseconds
sleep 10
}