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Open source ARM Debugger
By enthusiasticgeek
#182635
I am trying to get 28F640J3 CFI external NOR flash interface to ks8695 (ARM922T core) show up in openocd. I am using Segger Jlink JTAG interface.

The flash banks are arranged in the 2 banks with 4 chips, each 64Mbit 8Mx8 which makes each chip 8MByte or total 8MByte x 4 = 32 MBytes, as shown in the image (hopefully the image url won't go down anytime soon!). The comment on the file below though states 'Each bank is 16-bits wide, two 16-bit chips in parallel'. It also has 32 MB SDRAM.

Image
Image

From the datasheet System configuration registers I found

0x3ff4000-0x3ff4040 are of our interest. I luckily found something for the board in archives which I thought would be of our interest
Code: Select all
//comment this is the board init configuration file
//comment which sets up the sdram and flash memory 
//comment so that user can download code into sdram
//comment and run it.
//comment This file is used to enabe the demo board
//comment when there is no code resides in the flash
//comment memory.

//comment set up external banks
//DEVICE ALE
//B31:22 = 3FC (end address = 0x3FCFFFF)
//B21:12 = 3FC (start address = 0x3FC0000)
dword(0x03FF4000) = 0xFF3FCFFF
//DEVICE RD
//B31:22 = 3FD (end address = 0x3FDFFFF)
//B21:12 = 3FD (start address = 0x3FD0000) 
dword(0x03FF4004) = 0xFF7FDFFF
//DEVICE WR
//B31:22 = 3FE (end address = 0x3FEFFFF)
//B21:12 = 3FE (start address = 0x3FE0000)
dword(0x03FF4008) = 0xFFBFEFFF

// *** Set up rom/flash  ***
//Bank 0
//B31:22 = 2FF (end address = 0x2FFFFFF)
//B21:12 = 200 (start address = 0x2000000)
dword(0x03FF4010) = 0xBFE00070 
//Bank 1
//B31:22 = 3FB (end address = 0x3FBFFFF)
//B21:12 = 300 (start address = 0x3000000)
dword(0x03FF4014) = 0xFEF00070

//External I/O and ROM/SRAM/FLASH General Register 
// Enable CAN RD, CAN WR and CAN ALE
dword(0x03FF4020) =   0x30FF000F 

// *** Set up SDRAM ***  
//SDRAM Control Register 0 (0x4030)
//B31:22 = 0FF (end address = 0xFFFFFF)
//B21:12 = 000 (start address = 0x0)
dword(0x03FF4030) = 0x3FC0000E 


//SDRAM Control Register 1 (0x4034)
//B31:22 = 1FF (end address = 0x1FFFFFF)
//B21:12 = 100 (start address = 0x1000000)
dword(0x03FF4034) = 0x7FD0000E 

dword(0x03FF4038) = 0x0000000A 


//comment send NOP command 
dword(0x03FF403C) = 0x00030000 
//comment wait for command to complete
//comment send precharge command
dword(0x03FF403C) = 0x00010000 
//comment wait for command to complete
dword(0x03FF4040) = 0x00000014 
//comment wait for command to complete
//comment set the refresh timer back
dword(0x03FF4040) = 0x00000168 
//comment wait for command to complete
//comment send Mode command
dword(0x03FF403C) = 0x00020033 //0x00020003
//comment set clock to be the fastest one
dword(0x03FF0004) = 0x00
 
//comment memory configured.
Based on this file I tried to write openocd file as follows and tweak 0x3ff4010,0x3ff4014 and 0x3ff4014 to get this CFI FLASH to recognized. After I tweaked 0x3ff4014 looking at the datasheet my bank 1 CFI would show up as two separate CFI chips since I used 4 'flash bank ....' commands because even though I have 2 banks - there are 4 chips 8 MByte each. I am not sure if my config below is correct. The start address for flash bank 0 is 0x02000000 and similarly for flash bank 1 is 0x03000000. When I run
Code: Select all
$: openocd -f enthusiasticgeek.cfg
#and in another window
$: telnet 127.0.0.1 4444
> reset init
> reset init; flash probe 0; flash probe 1  #<--------------Seems like it finds chip but unable to communicate with CFI driver  :(  :doh: 
... reset-start ....
adapter speed: 8 kHz
JTAG tap: ks869x.cpu tap/device found: 0x00922f0f (mfg: 0x787, part: 0x0922, ver: 0x0)
... reset-assert ....
srst pulls trst - can not reset into halted mode. Issuing halt after reset.
target state: halted
target halted in ARM state due to debug-request, current mode: System
cpsr: 0xe00000df pc: 0x00000038
MMU: disabled, D-Cache: disabled, I-Cache: disabled
... reset-init ....
... Executing procedure  acs5k_init_load_code_into_sdram....
... init routine ...
adapter speed: 8000 kHz
dcc downloads are enabled
NOTE! Severe performance degradation without fast memory access enabled. Type 'help fast'.
Flash Manufacturer/Device: 0xf0d7 0x0089
Could not probe bank: no QRY
Try workaround w/0x555 instead of 0x55 to get QRY.
Could not probe bank: no QRY
auto_probe failed
in procedure 'flash'
> reset init; flash probe 2; flash probe 3  #<------------------------------------------------------ Seems to WORK!!! :dance: 
... reset-start ....
adapter speed: 8 kHz
JTAG tap: ks869x.cpu tap/device found: 0x00922f0f (mfg: 0x787, part: 0x0922, ver: 0x0)
... reset-assert ....
srst pulls trst - can not reset into halted mode. Issuing halt after reset.
target state: halted
target halted in ARM state due to debug-request, current mode: System
cpsr: 0xe00000df pc: 0x0000002c
MMU: disabled, D-Cache: disabled, I-Cache: disabled
... reset-init ....
... Executing procedure  acs5k_init_load_code_into_sdram....
... init routine ...
adapter speed: 8000 kHz
dcc downloads are enabled
NOTE! Severe performance degradation without fast memory access enabled. Type 'help fast'.
Flash Manufacturer/Device: 0x0089 0x0017
Flash Manufacturer/Device: 0x0089 0x0017
flash 'cfi' found at 0x03000000
Flash Manufacturer/Device: 0x0089 0x0017
Flash Manufacturer/Device: 0x0089 0x0017
flash 'cfi' found at 0x03800000

Code: Select all
#File: enthusiasticgeek.cfg
#Config file Author: enthusiasticgeek 
#June 2015
#To test the JTAG connection to the board one can simply run the 
#openocd -f /usr/local/share/openocd/scripts/interface/jlink.cfg -c "gdb_memory_map enable" -c "gdb_flash_program enable" -f /usr/local/share/openocd/scripts/target/ks869x.cfg

source [find interface/jlink.cfg]

#GDB can also flash my flash!
gdb_memory_map enable
gdb_flash_program enable

# ARM920T CPU

if { [info exists CHIPNAME] } {
   set  _CHIPNAME $CHIPNAME
} else {
   set  _CHIPNAME ks869x
}

if { [info exists ENDIAN] } {
   set  _ENDIAN $ENDIAN
} else {
   set  _ENDIAN little
}

if { [info exists CPUTAPID] } {
   set  _CPUTAPID $CPUTAPID
} else {
   set  _CPUTAPID 0x00922f0f
}

if { [info exists FLASHTAPID] } {
   set  _FLASHTAPID $FLASHTAPID
} else {
   set  _FLASHTAPID 0x890017
}

debug_level 3

# telnet and gdb_ports
telnet_port 4444
gdb_port 3333

reset_config trst_and_srst srst_pulls_trst

# set adapter_nsrst_delay to the delay introduced by your reset circuit
# the rest of the needed delays are built into the openocd program
adapter_nsrst_delay 260
# set the jtag_ntrst_delay to the delay introduced by a reset circuit
# the rest of the needed delays are built into the openocd program
jtag_ntrst_delay 250

adapter_khz 4

# jtag scan chain
# Add new test access port
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID

#set CPU target name
set _TARGETNAME $_CHIPNAME.cpu

target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME 
#-variant arm922t

#Internal SRAM work area (typically equivalent L1,L2,L3 caches in x86)
$_TARGETNAME configure -work-area-phys 0x20000 -work-area-size 0x20000 -work-area-backup 0

# speed up memory downloads
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable

#foreach t [jtag names] {
#    puts [format " ======= TAP Found: %s =======\n" $t]
#}

$_TARGETNAME configure -event "reset-assert" {
        echo "... reset-assert ...."
        #cortex_a dbginit
}


$_TARGETNAME configure -event "reset-start" {
        echo "... reset-start ...."
	adapter_khz 8 
}

$_TARGETNAME configure -event "reset-init" {
        echo "... reset-init ...."
        echo "... Executing procedure  _init_load_code_into_sdram...."
	_init_load_code_into_sdram
}

#####################
# CFI Flash configuration
#####################


# flash bank <driver> <base> <size> <chip_width> <bus_width>
# CS0, CS1 -- two banks of CFI flash, 16 MBytes each
# each bank is 16-bits wide, two 16-bit chips in parallel
set _FLASHNAME $_CHIPNAME.flash0
flash bank $_FLASHNAME cfi 0x02000000 0x0800000 2 2 $_TARGETNAME 
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME cfi 0x02800000 0x0800000 2 2 $_TARGETNAME
set _FLASHNAME $_CHIPNAME.flash2
flash bank $_FLASHNAME cfi 0x03000000 0x0800000 2 2 $_TARGETNAME 
set _FLASHNAME $_CHIPNAME.flash3
flash bank $_FLASHNAME cfi 0x03800000 0x0800000 2 2 $_TARGETNAME


init

proc _init_load_code_into_sdram { } {
  
        echo "... init routine ..."

	#this is the board init configuration file
	#which sets up the sdram and flash memory 
	#so that user can download code into sdram
	#and run it.
	#This file is used to enabe the demo board
	#when there is no code resides in the flash
	#memory
	adapter_khz 8000
	arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads

	#Time to set up the SDRAM and Flash memory
	#comment set up external banks
	#CAN ALE
	#B31:22 = 3FC (end address = 0x3FCFFFF)
	#B21:12 = 3FC (start address = 0x3FC0000)
	#dword(0x03FF4000) = 0xFF3FCFFF
        mww 0x03ff4000 0xff3fcfff
	#CAN RD
	#B31:22 = 3FD (end address = 0x3FDFFFF)
	#B21:12 = 3FD (start address = 0x3FD0000) 
	#dword(0x03FF4004) = 0xFF7FDFFF
        mww 0x03ff4004 0xff7fdfff
	#CAN WR
	#B31:22 = 3FE (end address = 0x3FEFFFF)
	#B21:12 = 3FE (start address = 0x3FE0000)
	#dword(0x03FF4008) = 0xFFBFEFFF
        mww 0x03ff4008 0xffbfefff

        #======================================================================
        #################### MOST IMPORTANT TO BURN IMAGE #####################
        #======================================================================
	# *** Set up rom/flash  ***
        #======================================================================
	#Bank 0
	#B31:22 = 2FF (end address = 0x2FFFFFF)
	#B21:12 = 200 (start address = 0x2000000)
	#dword(0x03FF4010) = 0xBFE00070 
        mww 0x03ff4010 0xbfe00070
	#Bank 1
	#B31:22 = 3FB (end address = 0x3FBFFFF)
	#B21:12 = 300 (start address = 0x3000000)
	#dword(0x03FF4014) = 0xFEF00070
        mww 0x03ff4014 0xfef00070

	#External I/O and ROM/SRAM/FLASH General Register 
	# Enable CAN RD, CAN WR and CAN ALE
	#dword(0x03FF4020) =   0x30FF000F 
        #mww 0x03ff4020 0x30ff000f
        mww 0x03ff4020 0x30ff000a  
        #======================================================================

        #======================================================================
	# *** Set up SDRAM ***  
        #======================================================================
	#SDRAM Control Register 0 (0x4030)
	#B31:22 = 0FF (end address = 0xFFFFFF)
	#B21:12 = 000 (start address = 0x0)
	#dword(0x03FF4030) = 0x3FC0000E 
        mww 0x03ff4030 0x3fc0000e

	#SDRAM Control Register 1 (0x4034)
	#B31:22 = 1FF (end address = 0x1FFFFFF)
	#B21:12 = 100 (start address = 0x1000000)
	#dword(0x03FF4034) = 0x7FD0000E 
        mww 0x03ff4034 0x7fd0000e

        # Set global RAS/CAS timing
	#dword(0x03FF4038) = 0x0000000A 
        mww 0x03ff4038 0x0000000a
        #======================================================================


	#comment send NOP command 
	#dword(0x03FF403C) = 0x00030000 
        mww 0x03ff403c 0x00030000
	#comment wait for command to complete
	#comment send precharge command
	#dword(0x03FF403C) = 0x00010000 
        mww 0x03ff403c 0x00010000
	#comment wait for command to complete
	#dword(0x03FF4040) = 0x00000014 
        mww 0x03ff4040 0x00000014
	#comment wait for command to complete
	#comment set the refresh timer back
	#dword(0x03FF4040) = 0x00000168 
        mww 0x03ff4040 0x00000168
	#comment wait for command to complete
	#comment send Mode command
	#dword(0x03FF403C) = 0x00020033 #0x00020003
        mww 0x03ff403c 0x00020033
	#comment set clock to be the fastest one
	#dword(0x03FF0004) = 0x00
        mww 0x03ff4004 0x00000000
	 
	halt
	#flash probe 0                     ;# Identify flash bank 0

}

#Important URLs 
#http:#translate.google.com/translate?hl=en&sl=ja&u=http:#sonare.jp/wiki/%3FBLR-TX4M&prev=search
#https:#github.com/rhuitl/uClinux/blob/master/tools/misc/sg310.gdb


I am wondering why bank 0 cannot be found while seemingly bank 1 is found? Also I suspect my settings for NOR registers may be incorrect or may need some more tweaking. Any help is appreciated.
By enthusiasticgeek
#182655
Okay I made progress today :dance: . I realized my mistake. I just need 2 banks and not 4. Most importantly, I overlooked the fact that data bus is 32 bit and not 16 bit. I had to change the following.
Code: Select all
# flash bank <driver> <base> <size> <chip_width> <bus_width>
# (64Mbit = 8Mx8 = 8MByte) x 4 chips (i.e. 2 chips per bank) = 32 MBytes Total
# each bank is 16-bits wide, two 16-bit chips in parallel, 32-bit data bus (BTW, Address bus is 22 bit)
set _FLASHNAME $_CHIPNAME.flash0
flash bank $_FLASHNAME cfi 0x02000000 0x01000000 2 4 $_TARGETNAME
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME cfi 0x03000000 0x01000000 2 4 $_TARGETNAME
Similarly, I had to ensure all NOR FLASH registers matched 32 bit data bus. :D
Code: Select all

	#Bank 0
	#B31:22 = 2FF (end address = 0x2FFFFFF)
	#B21:12 = 200 (start address = 0x2000000)
	#dword(0x03FF4010) = 0xBFE00070 
        mww 0x03ff4010 0xbfe00070
	#Bank 1
	#B31:22 = 3FB (end address = 0x3FBFFFF)
	#B21:12 = 300 (start address = 0x3000000)
	#dword(0x03FF4014) = 0xFEF00070
        mww 0x03ff4014 0xfef00070

	#External I/O and ROM/SRAM/FLASH General Register 
	# Enable CAN RD, CAN WR and CAN ALE
	#dword(0x03FF4020) =   0x30FF000F 
        mww 0x03ff4020 0x30ff000f
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