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Open source ARM Debugger
By veli_joza
Hi everyone.

I'm using OpenOCD with BusPirate as JTAG interface to program and debug LPC4357 micro-controller. This chip has a Cortex M4 core, and a secondary Cortex M0 core. I have successfully used this configuration with M4 core (with M0 target creation disabled), but M0 core gives me troubles.

This is my OpenOCD configuration:
Code: Select all
source [find target/swj-dp.tcl]

adapter_khz 1000

if { [info exists CHIPNAME] } {
} else {
    set _CHIPNAME lpc43xx

if { [info exists M4_JTAG_TAPID] } {
} else {
    set _M4_JTAG_TAPID 0x4ba00477

if { [info exists M4_SWD_TAPID] } {
} else {
    set _M4_SWD_TAPID 0x2ba01477

if { [using_jtag] } {
    set _M4_TAPID $_M4_JTAG_TAPID
} {
    set _M4_TAPID $_M4_SWD_TAPID

if { [info exists M0_JTAG_TAPID] } {
} else {
    set _M0_JTAG_TAPID 0x0ba01477

swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M4_JTAG_TAPID
swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M0_JTAG_TAPID

target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0
target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4

set _WORKAREASIZE 0x2000
$_CHIPNAME.m4 configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE

flash bank flashA lpc2000 0x1a000000 0x80000 0 0 $_CHIPNAME.m4 lpc4300 107000 calc_checksum
flash bank flashB lpc2000 0x1b000000 0x80000 0 0 $_CHIPNAME.m4 lpc4300 107000 calc_checksum

cortex_m reset_config vectreset
On powering up and starting OpenOCD, the cores are reported correctly:
TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
0 lpc43xx.m0 cortex_m little lpc43xx.m0 reset
1* lpc43xx.m4 cortex_m little lpc43xx.m4 halted
Trying to use GDB's load command to write something to internal flash will give following error:
Error: timed out while waiting for target halted
TARGET: lpc43xx.m0 - Not halted
in procedure 'reset'
in procedure 'ocd_bouncer'

in procedure 'reset'

Error: Target not halted
Error: failed erasing sectors 0 to 3
Error: flash_erase returned -304
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x41000000 pc: 0x10402d5e msp: 0x10089c70, semihosting
Info : Halt timed out, wake up GDB.
Now I suspect the problem is that OpenOCD thinks it has to halt the M0 core, and that core is not responding to halt request. The reason for this is that M0 core is not even running and cannot be halted. Its reset and clock signals are controlled by M4 core and they are enabled only later in boot sequence.

Is there a way to tell OpenOCD that M0 core is not under it's control until after it's enabled by M4 firmware?

BTW if I load everything into RAM, everything behaves more or less correctly and I'm able to debug both cores independently from two GDB instances connected to 3333 and 3334 ports.
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