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[harish kumar]

Dear All,

Cortex-A memory write via AHB-AP invalidates I/D cacheline with physical address when Linux OS is running (MMU enabled).

In(OpenOCD 0.8.0), the file “src/target/cortex-a.c”, lines 2235 & 2252, uses physical address whereas Cortex-A8 specification mentions the usage of virtual address. This results in error during memory write request from OpenOCD while Linux kernel is up-and-running.

Any thoughts?

Thanks and Regards,
Harish Kumar V

[harish kumar]

Dear All,

An update.

My setup: Linux is up-and-running on my target HW (Cortex-A8 based). Now via the debugger, a halt command is issued. Thereafter, using the debuggers memory window, I try to change the value of a global variable (virtual address) using “mww <virtual address> <value>”. Target HW uses AHB-AP path.

Currently, Cortex-A memory write via AHB-AP invalidates I/D cacheline with physical address when Linux OS is running (MMU enabled).

But, as per Cortex-A8 TRM [http://infocenter.arm.com/help/index.jsp], it should be virtual address.
Cortex-A series processors -> Cortex-A8 -> Revision: r3p2 -> Cortex-A8 TRM -> System Control Co-processor -> System Control Co-processor registers -> c7, Cache operations -> Data formats for the cache operation -> MVA

Current implementation in Openocd :
-----------------------------------------
if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
LOG_DEBUG("Writing memory to address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address, size,
count);
if (mmu_enabled) {
virt = address;
retval = cortex_a8_virt2phys(target, virt, &phys);
if (retval != ERROR_OK)
return retval;

LOG_DEBUG("Writing to virtual address. Translating v:0x%" PRIx32 " to r:0x%" PRIx32,
virt,
phys);
address = phys;
}
retval = cortex_a8_write_phys_memory(target, address, size,
count, buffer);
}

In cortex_a8_write_phys_memory(), from line 2213 to 2264, does, Invalidating I/D cacheline.

Proposed implementation :
------------------------------
if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
LOG_DEBUG("Writing memory to address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address, size,
count);
if (mmu_enabled) {
virt = address;
retval = cortex_a8_virt2phys(target, virt, &phys);
if (retval != ERROR_OK)
return retval;

LOG_DEBUG("Writing to virtual address. Translating v:0x%" PRIx32 " to r:0x%" PRIx32,
virt,
phys);
address = phys;
}
retval = cortex_a8_write_phys_memory(target, address, size,
count, buffer);
if (retval == ERROR_OK && mmu_enabled)
retval = cortex_a8_invalidate_cache_mva_pou(target, virt, size, count);
}

Move from cortex_a8_write_phys_memory(), from line 2213 to 2264, does, Invalidating I/D cacheline to cortex_a8_invalidate_cache_mva_pou()

Any thoughts on this ?

Thanks and Regards,
Harish Kumar V