SparkFun Forums

[jqpublick]

When issuing a "reset" from OpenOCD, what exactly is happening? Does this simply pull down the SRST line and nothing else?

What is the difference between "reset halt" and "soft_reset_halt"?

- Joe

[Dominic]

See http://openfacts.berlios.de/index-en.ph ... D_commands

A 'reset' without an argument uses the behaviour specified in the 'target ...' line, i.e. if your target line looked like this:
target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4

the 'reset' command would actually be 'reset run_and_halt'.

The reset behaviours "halt" and "init" are only available when it's possible to halt the target directly out of reset. This works for AT91SAM7 chips for example, but not for LPC2000 chips.

'soft_reset_halt' only works when the target is currently halted, and fakes a reset by setting the PC to 0x0, switching to SVC mode and disabling MMU/Caches in case of a ARM720t or ARM920t system.

Regards,

Dominic

[jqpublick]

reset ['run'|'halt'|'init'|'run_and_halt'|'run_and_init']
Do a hard-reset. The optional parameter specifies what should happen after the reset. This optional parameter overwrites the setting specified in the configuration file, making the new behaviour the default for the 'reset' command.

What is meant by a "hard-reset"? In the AT91SAM7_, the reset pin (which is typically connected to the JTAG SRST line) is disabled by default. If the processor's reset line is disabled, there must be some other instruction telling the core to halt and reset.

This may explain what I am seeing: The core halts, but since the rest of the processor never gets the reset signal, none of the peripherals are reset. The soft_reset_halt doesn't reset the peripherals either.

What I would like to achieve with OpenOCD is a "reset" that is identical to a power-on reset, with the processeor in it's default startup mode, halted, waiting to run the first instruction at 0x0. Must I have the reset pin enabled to do this sort of reset over JTAG?

- Joe

[Dominic]

Hello Joe,

hard-reset means asserting the nSRST pin, soft-reset means "simulating" a reset (see description of the soft_reset_halt halt command).

I wasn't aware of the AT91SAM7 feature to "disable" the reset line. If you want to be able to reset these devices, you'll have to manually enable the reset line.

I've just checked with a AT91SAM7S64, and the demo code running on the board obviously had URSTEN set in the RSTC_MR. With that setup, I could use "reset halt" to force the target into debug mode right out of reset. Reading the RSTC_SR returned "User reset" as the reset type.

Regards,

Dominic