I would like to build a OOCDLink http://www.joernonline.de/contrexx2/cms ... p?page=126
and I'm interested in the "high speed" variation of the design (OOCDLink-H) using the faster FT2232H (as opposed to the slower FT2232D). I want to modify the circuit to include a buffer chip or level shifter chip such as the MAX13013. These level shifters have an "ENABLE" pin that will bring both side's IO to tri-state when disabled.
On the "low speed" variation of the OOCDLink design using the FT2232D, there is a level shifter and its "ENABLE" pin is connected to a signal "ADBUS4".
On the "high speed" variation of the OOCDLink design using the FT2232H, there are two buffer chips on TRST and SRST whose ENABLE pins are connected to pins on GPH0 and GPH2.
I'm trying to find out where to connect to connect the ENABLE pins of the MAX13013 level shifters I plan to add into the high speed design. Maybe I can tap into one of the ENABLE signals for TRST or SRST?
Or leave them always enabled? The target of the JTAG usually have pull-up resistors so this is only a good idea if the FT2232 leaves pins high while idle.
-EDIT: I'm confused, I just saw Opendous's JTAG design here http://code.google.com/p/opendous/wiki/JTAG
and the pin connections are completely different. I think I'll copy that design instead but I'm going to try to understand OpenOCD handles the different FT2232H based designs