OOCDLink-H, add buffer to design

Open source ARM Debugger

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OOCDLink-H, add buffer to design

Postby frank26080115 » Mon Dec 20, 2010 1:09 pm

I would like to build a OOCDLink http://www.joernonline.de/contrexx2/cms ... p?page=126 and I'm interested in the "high speed" variation of the design (OOCDLink-H) using the faster FT2232H (as opposed to the slower FT2232D). I want to modify the circuit to include a buffer chip or level shifter chip such as the MAX13013. These level shifters have an "ENABLE" pin that will bring both side's IO to tri-state when disabled.

On the "low speed" variation of the OOCDLink design using the FT2232D, there is a level shifter and its "ENABLE" pin is connected to a signal "ADBUS4".

On the "high speed" variation of the OOCDLink design using the FT2232H, there are two buffer chips on TRST and SRST whose ENABLE pins are connected to pins on GPH0 and GPH2.

I'm trying to find out where to connect to connect the ENABLE pins of the MAX13013 level shifters I plan to add into the high speed design. Maybe I can tap into one of the ENABLE signals for TRST or SRST?

Or leave them always enabled? The target of the JTAG usually have pull-up resistors so this is only a good idea if the FT2232 leaves pins high while idle.

-EDIT: I'm confused, I just saw Opendous's JTAG design here http://code.google.com/p/opendous/wiki/JTAG and the pin connections are completely different. I think I'll copy that design instead but I'm going to try to understand OpenOCD handles the different FT2232H based designs
Recently graduated from UW for EE!
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Re: OOCDLink-H, add buffer to design

Postby AMONTEC » Tue Dec 21, 2010 12:47 am

Hi,

You should use Amontec JTAGkey layout and use the JTAG_OE_N signal.
Please see http://www.amontec.com/jtagkey.shtml . On the middle of the page you can found a .pdf with the layout used by all Amontec JTAGkey USB JTAG Cables.

Note Amontec JTAGkey-2 is fully compatible with Amontec JTAGkey(-1) but comes with FT2232H instead FT2232D. The high-speed USB version of FT2232 family.

The JTAGkey dongle serie are UNIQUE since they come with UHS buffers, with Ultra High Speed buffer providing 32mA output driver !

The UHS drivers are a little bit expensive regarding simple 244 but make the 30Mhz JTAG frequency possible.

Amontec JTAGkey-2P has the possibility to provide a regulated VDD 3.3V on pin 19 on the 20-pin connector, like the ST-LINK JTAG dongle. This make possible to power your target board for production line, or power some specific JTAGkey adapter as an isolator, without adding any DC/DC regulator ...

Amontec is working on JTAGkey-3 with SWD support and much more, but still backward compatible with JTAGkey and JTAGkey-2 ;-) !

Laurent
http://www.amontec.com
AMONTEC
 
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Re: OOCDLink-H, add buffer to design

Postby frank26080115 » Tue Dec 21, 2010 12:59 am

ohh cool i just realized the design i'm copying is pin-pin compatible with your JTAG Key, which probably means i don't have to recompile OpenOCD

sorry but 129 euros is way too expensive, cool stuff though, thanks for the info
Recently graduated from UW for EE!
frank26080115
 
Posts: 237
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Re: OOCDLink-H, add buffer to design

Postby AMONTEC » Tue Dec 21, 2010 2:46 am

Check Amontec JTAGkey-2 OEM at €75.- ;-) The JTAGkey-2 without flying lead cable, without flat cable, with certified hi-speed USB 2.0 1.8m cable, without box, without doc ...

but with
RTCK support
1.3V to 5.5V JTAG IO auto-sense
32ma buffer at 3.3V
hot-plug JTAG
hot-plug USB

http://www.amontec.com
AMONTEC
 
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