stm32 and altera cpld in a jtag chain

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stm32 and altera cpld in a jtag chain

Postby rooks » Fri Feb 05, 2010 7:22 am

Is there any guide for creating a configuration file for the case when stm32 is not the only device in a jtag chain? In my chain altera epm240 goes first and is programmed ok from Quartus. Quartus also recognizes stm32 processor (stm32f103vct6). When I try to upload the program to the stm32 using the cfg file that worked ok when stm32 was the only device in chain, I get the following errors:
Error: JTAG scan chain interrogation failed: all ones
Error: Check JTAG interface, timings, target power, etc.
Thank you
rooks
 
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Joined: Fri Feb 05, 2010 7:05 am

Postby rooks » Sun Feb 07, 2010 2:00 am

The errors from the first post were due to a connection error. Now, when it was solved, I get the following output

Warn : use 'stm32.cpu' as target identifier, not '0'
Info : clock speed 500 kHz
Info : JTAG tap: stm32.cpu tap/device found: 0x3ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x3)
Info : JTAG tap: stm32.bs tap/device found: 0x06414041 (mfg: 0x020, part: 0x6414, ver: 0x0)
Warn : Invalid ACK in SWJDP transaction
Warn : Invalid ACK in SWJDP transaction
Warn : Invalid ACK in SWJDP transaction
Warn : Invalid ACK in SWJDP transaction
Warn : Block read error address 0xe000ed00, count 0x1
Warn : Invalid ACK in SWJDP transaction
Info : JTAG tap: stm32.cpu tap/device found: 0x3ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x3)
Info : JTAG tap: stm32.bs tap/device found: 0x06414041 (mfg: 0x020, part: 0x6414, ver: 0x0)
Warn : Invalid ACK in SWJDP transaction
Warn : Invalid ACK in SWJDP transaction
Warn : Invalid ACK in SWJDP transaction
Warn : Invalid ACK in SWJDP transaction
Warn : Invalid ACK in SWJDP transaction
expected return code but got 'TARGET: stm32.cpu - Not halted'
Runtime error, file "openOCD_STM32E.cfg", line 13:
rooks
 
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Joined: Fri Feb 05, 2010 7:05 am

Postby rooks » Mon Feb 08, 2010 8:48 am

I was lazy and didn't want to dig into the details but...

First autoprobing helped to find out the jtag id and irlen for the cpld
Code: Select all
source [find interface/olimex-arm-usb-tiny-a.cfg]
reset_config trst_and_srst
jtag_rclk 8

Output of these commands:
Code: Select all
Info : RCLK (adaptive clock speed) not supported - fallback to 8 kHz
Warn : There are no enabled taps.  AUTO PROBING MIGHT NOT WORK!!
Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x3ba00477 ..."
Warn : AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x06414041 ..."
Warn : AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x020a10dd ..."
Warn : AUTO auto0.tap - use "... -irlen 4"
Warn : AUTO auto1.tap - use "... -irlen 5"
Warn : AUTO auto2.tap - use "... -irlen 4"
Error: IR capture error at bit 13, saw 0x3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAA211 not 0x...3
Info : JTAG tap: auto0.tap tap/device found: 0x3ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x3)
Info : JTAG tap: auto1.tap tap/device found: 0x06414041 (mfg: 0x020, part: 0x6414, ver: 0x0)
Info : JTAG tap: auto2.tap tap/device found: 0x020a10dd (mfg: 0x06e, part: 0x20a1, ver: 0x0)
Error: IR capture error at bit 13, saw 0x2211 not 0x...3
Warn : no gdb ports allocated as no target has been specified

There is an error with IR capture here and the same error appeared when trying to upload data to the flash with a new tap created. This error was solved by changing IRLEN in tap declaration. It is 10 bits not 4 as autoprobing states. I got the following output:
Code: Select all
Info : JTAG tap: stm32.cpu tap/device found: 0x3ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x3)
Info : JTAG tap: stm32.bs tap/device found: 0x06414041 (mfg: 0x020, part: 0x6414, ver: 0x0)
Info : JTAG tap: EPM240.cpld tap/device found: 0x020a10dd (mfg: 0x06e, part: 0x20a1, ver: 0x0)
Info : Halt timed out, wake up GDB.
Error: timed out while waiting for target halted
expected return code but got 'TARGET: stm32.cpu - Not halted'
Runtime error, file "openOCD_STM32E.cfg", line 14:

This error is due to reset misconfiguration. On my board SRST was not routed. After connecting SRST to the CPU everything worked just fine.
Now I have a question how to halt the CPU without using SRST. Could anyone please share any examples on how to use reset-assert event handler?
rooks
 
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Joined: Fri Feb 05, 2010 7:05 am

Postby ntfreak » Tue Feb 09, 2010 7:31 am

If you do not want to use srst then just tell openocd
reset_config trst_only

to use scripts have a look in the tcl directory, brief example:
assuming your target is called my_target.
Code: Select all
my_target configure -event reset-assert {
    # do stuff here
}
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