Vintage CPU + external parallel flash + OpenOCD: Feasible? Pointers?

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jaholmes
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Joined: Mon May 03, 2010 11:47 am

Vintage CPU + external parallel flash + OpenOCD: Feasible? Pointers?

Post by jaholmes » Wed May 16, 2018 7:59 am

Long story short(-ish): I'm working on a pair of SBC designs based on vintage (1980's) MPUs and am contemplating how best to accomplish in-system programming of flash memories for program storage. A few proprietary (and arguably more straightforward) ways have come to mind, but it seemed to me that using JTAG might be the "cool" way to do it while also providing for circuit verification/debugging. In my travels since, I've stumbled upon a few possibly-relevant ICs, notably the TI SN74BCT8245, which is a 74xx245 bus transceiver with boundary scan. This got me wondering: Could I simply array these on the address and data buses and use them (as a single logical shift register) to program flash?

Technically, I can see no reason why this wouldn't be possible, but sifting through the OpenOCD docs has left me scratching my head a bit--actually, a lot! Most of the documentation and examples surrounding OpenOCD/JTAG programming of flash memories seem (understandably) geared toward more modern targets, like CPUs with boundary scan and MCUs with integrated flash. I guess I'm hoping somebody can refer me to a lower-level example or tutorial where pin/bus mappings are generally defined (ideally without assuming that all of the pins on the memory bus reside on a single TAP) and then used for programming. I'm 99.9% sure that such a thing exists, but for my particular aim, I'm finding that the signal-to-noise ratio is a tad low.

(Also: Responses like, "What the heck? Why would you bother to do that?" are totally appreciated also.)

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