- Sat Oct 05, 2019 12:28 pm
Getting to the root of "6 uA per MHz":
Take a look at the clock diagram in the Apollo3 data sheet. If you zoom in on the part at the bottom showing where the CPU gets its clock (attached), you can see that the signal marked "hclk/fclk to CPU/SRAM/Cache" only has two possible frequencies that can be selected from the multiplexer: 48 MHz or 96 MHz. There are a total of three various divider blocks in the original diagram (only one of them is visible in the attachment), but none of the three has an output that goes to the processor/SRAM/cache. The upshot is that when the data sheet says "6 uA per MHz", there is an implicit multiplier of 48 because the slowest the processor can run is 48 MHz. So: the lowest typical current draw that a running program could have would be 6 uA/MHz *48 MHz, or 288 uA.
In regards to a comment way earlier in this thread about a processor "running at 3 MHz", it is clear that something inside the processor might have been getting clocked at 3 MHz, but it couldn't have been the processor itself.
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