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By robin_hodgson
#208302
A JLink EDU ($60 from Sparkfun). My understanding is that the setup will also work with a JLink EDU Mini ($18 at Sparkfun), it will just be a bit slower than the more expensive one.
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By VA3SU
#208303
Much better than the ~$400-$900 dollar ones lol. BTW my Redboard draws 2.48-2.54uA and it doesn't change when on or off the bench held in hand etc. Warming it up with fingers brings it above 2.6uA breath about the same. Using a Rigol DM3058e no averaging.
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By robin_hodgson
#208329
Getting to the root of "6 uA per MHz":

Take a look at the clock diagram in the Apollo3 data sheet. If you zoom in on the part at the bottom showing where the CPU gets its clock (attached), you can see that the signal marked "hclk/fclk to CPU/SRAM/Cache" only has two possible frequencies that can be selected from the multiplexer: 48 MHz or 96 MHz. There are a total of three various divider blocks in the original diagram (only one of them is visible in the attachment), but none of the three has an output that goes to the processor/SRAM/cache. The upshot is that when the data sheet says "6 uA per MHz", there is an implicit multiplier of 48 because the slowest the processor can run is 48 MHz. So: the lowest typical current draw that a running program could have would be 6 uA/MHz *48 MHz, or 288 uA.

In regards to a comment way earlier in this thread about a processor "running at 3 MHz", it is clear that something inside the processor might have been getting clocked at 3 MHz, but it couldn't have been the processor itself.
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By robin_hodgson
#208338
All industry datasheets involve a certain amount of specmanship.

I did find something else this morning. It would appear that there is a master clock divider for HFRC where it can be divided by 2, if desired. See attached register description. The diagram of clock sources in the data sheet does not show an HFRC master divider, but if so, the processor would be capable of running at 96 MHz, 48 MHz, or 24 MHz. I'll try to verify that today.
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By robin_hodgson
#208339
Yup, it's confirmed that the core clock divisor works as described. Running a while (1); at 24 MHz drops the current to about 60% of the current at 48 MHz. As always, running at 24 MHz means that it will take twice as long to perform the same set of instructions than running at 48 MHz, so while the peak current consumption will be lower at 24 MHz, the energy consumed to perform an identical set of instructions is actually higher at 24 MHz than 48 MHz.