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User avatar
By SidPrice
#225995
I recently needed to convert the blocking use of I2C (IOM5) on the project I have. The issue I am facing is the ISR for IOM5 is never called even though the transfer is being completed and the interrupt status flags appear to be set in IOM5 interrupt status register.

Interrupts are being enabled in "am_hal_iom_nonblocking_transfer", my ISR looks like this:
Code: Select all
void am_iomaster5_isr(void)
{
    uint64_t ui64Status;
    traceISR_ENTER();
    am_hal_iom_status_get(&g_I2C5Handle, &ui64Status);
    am_hal_iom_interrupt_clear(&g_I2C5Handle, ui64Status);
    am_hal_iom_interrupt_service(g_I2C5Handle, ui64Status);
    traceISR_EXIT();
}
IOM5 is configured:
Code: Select all
static am_hal_iom_config_t g_sIOMI5cConfig =
    {
        .eInterfaceMode = AM_HAL_IOM_I2C_MODE,
        .ui32ClockFreq = AM_HAL_IOM_400KHZ,
        .pNBTxnBuf = i2c5OutputBuffer,
        .ui32NBTxnBufLength = sizeof(i2c5OutputBuffer)/4,
        };
Interrupt priority is set and IOM5 is enabled:
Code: Select all
    //
    // Initialize IOM 5.
    //
    am_hal_iom_initialize(iomModule, &g_I2C5Handle);

    am_hal_iom_power_ctrl(g_I2C5Handle, AM_HAL_SYSCTRL_WAKE, false);
    //
    // Set the required configuration settings for the IOM.
    //
    am_hal_iom_configure(g_I2C5Handle, &g_sIOMI5cConfig);
    //
    // Configure the IOM pins.
    //
    am_bsp_iom_pins_enable(iomModule, AM_HAL_IOM_I2C_MODE);
    //
    // Set the IOM Interrupt priority
    //
    NVIC_SetPriority(IOMSTR5_IRQn, I2C_5_INTERRUPT_PRIORITY);
    //
    // Enable the IOM.
    //
    am_hal_iom_enable(g_I2C5Handle);
I am at a bit of a loss as to what could be wrong.
Sid
User avatar
By WilliamHilbert
#226583
the non-blocking communication, the CPU will not wait until each byte is transferred, but the algorithm allows the C ISR Callback when the master is in receiving mode (read data message) example showing the way how to use it in the application. C module on the MCU, function is called from the I2C_Restore().
www.upsers.com
User avatar
By Dr. T.
#231124
Hi, just a quick thought: SPI/I2C communication is based on FIFOs in the apollo3. I haven't looked into the hal-code for I2C communication (I am using may my own hal-layer), but it could be that 'non-blocking' means that the data (up to 32 or 64 bytes?) is written into the FIFO and the transfer is started with a single write operation to the command register. This way the control is immediately returned to the calling function, and the I2C transfer is performed in parallel, without the use of a ISR. This could explain why the ISR is never called.
BTW: I was using this method when I ported some code for a MP3 decoder/player to apollo3: I had a timer-based ISR (typically with 41/48/64 KHz) putting the PCM values to a SPI-based DAC. The ISR was only putting the 16bit PCR value into the FIFO and starting the transfer - without waiting for the end of the transfer (this was not necessary because I knew the transfer would be finished before the next timer interrupt).
BR, Andreas
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