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Questions about the BatchPCB service

Moderator: robacarp

User avatar
By elevator4
#5113
Hi All,
my gerber files just got sent back again with a complaint that two LPC2106 pads had a clearance of less that 8 mils.
Since I had checked the design both with Protel's DRC (to 8mil clearances) and with Sparky's online checker before submitting them, I decided to take a closer look at what is happening.

Why only those two pads?
According to Protel, all pads on that IC have a clearance of 8.2 mils. Hmmm.
Protel does the DRC on the PCB design itself, *before* generating the gerbers and truncating the precision of coordinates in the process.
Here's what I found - I think the rounding of coordinate values is the culprit.
In fact, depending on the values of the pad coordinates and the method of rounding used, the clearance between pads can magically become less than 8 mils.

Here's an example of two fictuous pads (for clarity only X coordinates are used). The first case has the two pads at coordinates 100.3 and 118.1 respectively. Regardless of rounding method used, the resulting clearance is always 8.4 mils.
The second case has the same pads with the same pitch and width, but their nominal location is now 100.6 and 118.4 respectively, i.e. 0.3mils right of the first case.
When these coordinate values are rounded to the nearest mil, the clearance between the two pads now becomes just 7.4 mils --> Miserably FAIL Sparky's rigid internal DRC! :evil:

Case 1: Owing to their values, coordinates of both pads are rounded in the same direction
Code: Select all
                         nominal rnd-up rnd-down rnd-nrst
pad a center x coord	100.3    101      100         100
pad b center x coord	118.1    119      118         118
pad x width            9.6       9.6      9.6        9.6
pad center-to-center pitch 17.8 18        18           18
pad-to-pad clearance   8.2       8.4       8.4        8.4
Case 2: with "round-to-nearest", Pad a coord gets rounded up, Pad b coord gets rounded down.
Code: Select all
                         nominal rnd-up rnd-down rnd-nrst
pad a center x coord    100.6    101      100         101
pad b center x coord    118.4    119      118         118
pad x width             9.6      9.6      9.6        9.6
pad center-to-center pitch 17.8  18       18          17
pad-to-pad clearance    8.2      8.4       8.4       7.4
So much for the theory - I may be totally wrong but I'd like Sparky to confirm that this is what actually happens.

Anyway, here are two suggestions:
a) as was previously suggested in another post, design your board with 10mil width/clearance constraints to allow for roundoff errors in the process.
b) use a higher precision format in the gerber and drill files: 2.4 in inches, or 3.2 in millimeters.
I would much prefer b), because with a) all the nice the 0.5mm pitch ICs would be effectively outlawed. Also, it seems to me a pity not
to be able to take advantage of Gold Phoenix' full capabilities.
By pittuck
#5114
i think one of the reasons for the cheap price is the lack of precision... (Might be a we have an old machine how can we make money on it sort of thing)

Anyhow, at this time i cannot test pad spacing. There are a million and one reasons why and not not enought time to start. It would mean actually creating the PCB in a virtual memory and then manually checking every pixel of the image. Perhaps one day, but not today.

Thanks for the info, do u know the name of one of the layer files which had the problem? I will download it and put it in a safe place for 'later' examinations !
By Caffeine
#5117
I found when using protel (DXP) that switching back and forth between metric and imperial when I was laying out the PCB cause some rounding errors to creep into the clearances, it went from 8mil minimum to 7.87something clearance, which caused heaps of violations.

Protel 2004 doesn't seem to suffer from this problem
User avatar
By elevator4
#5118
pittuck,
I am not blaming your online DRC. In total ignorance it just puzzled me that the file passed Protel, passed your DRC but failed Ben's.
I agree with you that checking clearances is way harder than checking trace widths, and while it would certainly be the ultimate luxury, I am not suggesting it.
Instead, after what I found - and assuming I am correct - I believe that working with a higher precision would strongly mitigate, if not entirely solve, the problem. Remember that the rounding/truncating happens when my Protel generates the gerbers, so unless I have a way to do a final DRC on the gerbers before mailing them to catch the newly introduced clearance violations, Ben gets to discover the violations and send emails... and BTW that's where the economic viability factor for Sparkfun comes into play.

I think you agree that rounding off 1/8 (ie 1mil on 8mil constraints) is asking for trouble.
Is there a particular reason why the 2.3" format was mandated? I know some PCB houses (and/or CNC machines) don't like higher precisions (they just ignore the excess digits).
i think one of the reasons for the cheap price is the lack of precision...
:D Sounds like an inverted "you get what you pay for..." :D
But seriously, I very much appreciate Sparkfun's effort to provide a high-quality, low low cost PCB service and I understand that in order to be commercially viable, your overhead has to be as low as possible.
That's why I felt so miserable when the first submission failed because the layer and drill files were found to be off by inches: I never knew because my usual PCB fab house never complained - they'd just fix it - but then I was paying dearly for that service.
Well, I finally resolved to install service pack 6 on my old Protel, and yes Protel is another topic...
User avatar
By elevator4
#5119
pittuck,
the file name is scroll02.gtl, the top layer. I just had your DRC run on it - take the most recent instance of the file, the previous one is the corrected version.
Here are the questionable pads, in white.
Image
User avatar
By elevator4
#5120
Caffeine,
I (still) use 99SE and I agree it is sloppy with unit conversions. Makes me swear.
But this all happened on the gerbers, *after* the final DRC had passed, so I don't think I can blame the unit toggling.
Cheers
By pittuck
#5121
ok thanks, will download it in a while (i need to change the file permissions before i am able to download files ;))
User avatar
By sparky
#5136
Just to pipe in -

We use Protel DXP -> CAMtastic for all DRC checking.

We've seen this software do some really screwy stuff. It will generate all sorts of false DRC failures. Hundreds. We get to try to sort through them all.

Ground/plane pours are a big problem for camtastic. We usually ignore these <8mil errors.

Pin spacing is not something we can ignore. We get to go in by hand (ctrl+m I believe) and measure edge to gerber edge. Sometimes, these are false as well (spacing is actually ok).

Finally - CAMtastic seems to be importing the vectors oddly:
Here is a screen shot of a board with a 10mil grid, 10mil track width, 4mil 'min prim length' as it is shown in the protel layout:
Image

Here is the same file exported to gerbers in the CAMtastic software:
Image

Those small bumps in the middle kill the DRC. I believe the camtastic software is importing the vector widths incorrectly? Not sure.

Gold Phoenix is happy to run panels down to 6mil trace/spacing. To do this, they have to make multiple panels because some designs will fail QC. They charge an extra $40 per panel because of the extra materials and inspection.

I know what you're thinking : just change the spec to 6mil space/trace and eat the $40. The second we do this, customers will start sending us 4mil designs and we are right back where we started.

-Nathan
User avatar
By elevator4
#5145
Nathan,
thanks for the reply.
I'm not thinking of 6mil rules at all. If you read my original post I actually suggested designing with 10mil rules just to make it easier on you guys.
But more importantly, could you check if CAMtastic behaves differently when reading a gerber with coordinates in a 2.4 instead of 2.3 format?
I bet at least some DRC violations will go away.