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Questions about the BatchPCB service

Moderator: robacarp

By eejake52
#5084
I am using Eagle 4.14 and I got SILK_GEN.ULP v1.3 from Pyrankster's site. I am really close to having my first board ready for submission. I noticed that the SILK_GEN.ULP will not generate a wire from layer _tPlace if it is on top of a net from layer Top. Is that by design? What is the issue? Is there a workaround?
By eejake52
#5171
I was wrong about the source of the problem - it has nothing to do with silk on net.

The real problem is SILK_GEN.ULP ignores any wires in the tPlace layer. To fix this, open the ULP in the text editor, find subroutine board(B), then near the bottom of the routine,
change this:
Code: Select all
        // process source layers...
        for (i = 0; i < nLayers; i++) {
            setLayer(dst[i]);
            B.texts(T) {
                searchTexts(T,src[i]);
            }
            B.elements(E) {
                searchElements(E,src[i]);
            }
to this:
Code: Select all
        // process source layers...
        for (i = 0; i < nLayers; i++) {
            setLayer(dst[i]);
            B.texts(T) {
                searchTexts(T,src[i]);
            }
            B.wires(W) {
                searchWires(W,src[i]);
            }
            B.elements(E) {
                searchElements(E,src[i]);
            }
Now I am ready to submit this board.

Jake
By Pryankster
#5174
The wires objects are copied from the dimension layers, I'm not sure why I didn't copy them from the other layers. I seem to remember there being a reason, though ... I'll have to go back and look at the code...

(it may be as simple as "the original code didn't do it" :-) )

Thanks, I've added those lines to my copy, and updated the link on my web site: Silk Gen 1.4.

(note that the version number is my CVS version number, not some kind of release number)

-- Pryankster