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Eagle silk over SMD design rules?

Posted: Thu May 05, 2005 6:19 pm
by Oznog
I mentioned this on another thread that it can't be checked, figured I should check it out to be sure.

One of the most annoying problems I've seen with Eagle is finding places where the silkscreen of one component's name/value is on top of an SMD pad. It's not always easy to find at a glance if the board is complicated.

Looking at the dru file, I can specify clearance requirements between names/values and the Top layer, but the Top includes not only SMD pads but all the traces on top of the board. If they can't be separated then it can't be checked.

Is there any way to add this to the dru or not?

Posted: Thu May 12, 2005 3:01 pm
by sparky
My boiled down reply on the other post: it's not a problem. Try to avoid it, but gold phoenix doesn't care and you can almost certainly solder to the pad - the silkscreen will just burn off when the solder starts to liquify.


Posted: Thu May 12, 2005 7:22 pm
by tmbg
can you maybe have it check clearance between the silkscreen layer and the soldermask layer? Soldermask layer should show a pad but not a trace.

Posted: Mon May 23, 2005 7:55 am
by d0c
To the best of my knowledge, your pretty much stuck with manually locating the offending NAME/VALUE, then SMASHing the component in order to CHANGE => SIZE the text and/or MOVE the text to a more preferable location.

Not a biggie for small/simple boards, but with more complex boards, the chance of missing something while manually combing over the board (and the resulting surprise when your delivery from the board house arrives) is much greater.

Until Cadsoft incorporates an automatic feature to do this, a good practice to employ (if one is not pressed for time) is to walk away from the finished board layout, and come back in a couple days with a "fresh set of eyes" to review your layout...
You will be amazed at just how many glitches you end up spotting on what you thought was a clean board only a few days earlier!