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By ltk
#20476
Second draft won't work. With no signal, the output transistor will be on because its base is being pulled down to 6v.

The first design might be ok with 14.4v. You might need to increase the bias resistors. Say, double them.
By sparky3489
#20481
Change in design:

Image
By sparky3489
#20630
Does anyone forsee any problems with the previous diagram?
By sparky3489
#20657
or this one?

Image
By riden
#20661
A lot depends upon the gain of your transisters, but I would breadboard your circuit and see what tweaks are necessary for your componets. That is how I discovered a lot of the hows and whys of circuit design!

Note that when your second NPN transister turns on, it will be "shorting out" the 100uf capacitor, possibly exceeding the maximum collector current depending on how hard the NPN transister is driven. If I were building this, I'd place a smaller value capacitor (10uf?) on base of the NPN instead of the 100uf on the collector or add a current limiting resistor from the collector to the capacitor. Your mileage may vary.
By sparky3489
#20662
I got this design from the web and modified it, like so. Design #5:

Image
By sparky3489
#20703
Well crap!!

I found what I was looking for with no guess work involved. I'll still have to tweak it a bit, but I think I've got a handle on that.

Image

Image

So I would like to thank everyone who helped me out in my quest.

peace.