Mee_n_Mac wrote:TriBob wrote:I just realized that an awesome ADC simplification should be possible: Acquire ALL the ADCs ALL the time in burst mode, then in the DONE IRQ handler use the config file info to determine which ones get logged, and which get ignored.
Will you be sacrificing sampling rate for those times when all the channels aren't wanted ? N channels takes N times as long as 1 channel.
Not really: I plan to run acquisition at a fairly high rate, so that whenever you periodically read any ADC register, it is more recent than the last time you read it. Most people don't realize that 'perfect' ADC timing is rarely needed: 'Fast enough' is 'good enough' for the vast majority of cases, especially if the individual inputs aren't correlated (e.g., not measuring 2 aspects of a single signal, such as current and voltage, or I & Q amplitudes, or amplitude and phase).
For example, if I plan to read the ADC registers at 1 KHz, it doesn't matter if the ADC itself is running at 1 KHz or 1.1 KHz or 10 KHz or 100 KHz: The value in the register will always be 'fresher' than 1 KHz. Yes, it sounds sloppy, but getting rid of the need to synchronize to the ADC rate can free up lots of CPU time.
So, if I want 14 channels of data at 3200 Hz from 2 ADCs (8 from one and 6 from the other), I'd simply run both ADCs at a conversion rate of 26 KHz or higher. This scheme will work up to the max conversion rate of the ADC, which is a bit over 1 MHz for 10-bit data (or ~128 KHz/channel for 8 channels).
The ADCs seem to use very little power, so high sampling rates don't seem to have high power costs (though I don't yet have hard numbers for this). Getting rid of polling and ADC interrupts will let me use a simple timer interrupt, and also permit me to idle the processor between updates.
There are other possibilities to consider: I can use multiples of the desired sampling rate to increase the net sample width. I can sample at 2x my desired output rate, then use a single ADC 'done' interrupt to sum every pair of 10-bit samples to create an 11-bit output value. And if I wanted 12-bit data at 3200 Hz, I could run the ADCs at a 4x rate then sum 4 consecutive 10-bit samples to create each 12-bit sample. (That's one interrupt per SET of ADC conversions, not for each individual one.)
Unfortunately, the S/N can degrade faster than the bit depth increases (for a couple of reasons), so this technique is often self-limiting beyond a few bits of added resolution. (Adding 256 8-bit samples won't create a very good 16-bit value!) But I'm storing the data in 16-bits anyway, so increasing the bit depth a little beyond 10 bits can't hurt, especially if it is 'free'.