Since the TWI address range is only 0x07 to 0x70 (excluding reserved addresses, enumerated
here, It probably wouldn't take too long for a master to "poll" the entire address range, basically sending a START, SLA+R, STOP for each address, and check the ACK bit on the address byte to see if there's a device responding at that address.
After reading the data sheet a couple of times over, there are still some unanswered questions in my mind...
It seems like the only difference between a Master and a Slave on the bus, is that a master cannot be directly addressed. Seems like whatever device initiates a START condition automatically becomes a master (in a multi-master system). Nothing prevents a slave from initiating a START condition. Is this correct?
If so, the only problem here is that, in order for built-in arbitration to occur, all transmissions must contain the same number of data packets, which kind of sucks.
The datasheet makes several references to something called "Wired-ANDing" of the SCL line. Does this mean putting a transistor on the SCL line to ensure the clock signals match up (ie: smallest HI period, longest LOW period)? The datasheet doesn't make clear whether this is done internally to the AVR, or if I need to do this myself.
Some vocab: What is a "slew-rate limiter"?
The datasheet says that internal pullups on the TWI pins can be enabled by setting the right DDR and PORT values for those pins, and that "in some systems", this can remove the need for external pullups on the TWI lines. It's that "in some systems" that worries me. What is the value of these internal pullups? Come to that, what values do I need for pullups on these lines? I can't find the current draw requirements for TWI anywhere (maybe I'm asking the wrong question here...).
Although this is not explicitly stated in the datasheet, it looks like, when the last data byte is sent from a slave to a master (during a SLA read operation), the slave will signal this is the last byte by following up with a NACK. Is this part of the protocol?