SparkFun Forums

[HenningNT]

Hi all!

I'm sending 8192 bytes through nRF24L01, using Brennens library on ATMega168.

The bandwidth archived so far is 338kbit/s with auto ack, and 478 kbit/s without.

I've modified tutorial 2 heavily, and what I'm doing is basiclly a start and stop thing: Upload a packet. When IRQ fires, upload next packet, and so on... The CE line is never low, so the nRF24L01 goes from TX MODE to Standby-II, and back again.

However, I would like to have higher bandwidth. I want to poll the FIFO_STATUS register to see if the TX FIFO is full. If it it's not full, then I can upload a new packet, which gets transmitted as soon as the previous packet has been sent.

Like this:

Code: Select all

while ( count < NUM_PACKETS)
{
	while (!nrf24l01_fifo_tx_full())
	{
		// upload new packet
		datas[0] = count & 0xFF;	// low byte of counter
		datas[1] = (count >> 8);		//high byte of counter
		nrf24l01_write_tx_payload(datas, PAYLOAD_SIZE, false); //upload to nRF
		count++;
}
}

But it's not working Any suggestions?

The nrf24l01_fifo_tx_full() seems to return false wether or not the TX FIFO is full or not, so the program constantly pumps data into the nRF24L01 causing massive packet loss.

[brennen]

I looked through that function, and I can't see any problems with it from a code standpoint. You could try printing out the value of the FIFO_STATUS register that you're reading to see if the values look valid.

Another way to do what you're doing is to load up 3 packets to the TX FIFO to fill it up intitially, then start sending them. Then, when the IRQ fires, load one more packet up. That way, you'll always have a full buffer (until you've sent all the packets you want to send).

You aren't clearing the TX FIFO out in your code, are you? If you are calling nrf24l01_flush_tx() or nrf24l01_clear_flush(), this could be a problem.

[HenningNT]

Seems I didn't do the reception code properly. If I check RX FIFO and reads out data until it's empty, it looks like it's working. At least for three bytes