OpenOCD/GDB and Xilinx AXI2JTAG core

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PhilHays
Posts: 1
Joined: Sun Feb 24, 2019 9:53 am

OpenOCD/GDB and Xilinx AXI2JTAG core

Post by PhilHays » Sun Feb 24, 2019 10:09 am

I'm going to need to debug a processor in an FPGA without access to pins for attaching a JTAG dongle to.

Xilinx has an AXI4-Lite to JTAG core available. See:

https://www.xilinx.com/support/document ... alinux.pdf

I'd just be using the AXI2JTAG core, and not the "Virtual Cable" software. This is on a Xilinx FPGA, and is using a non-Xilinx supported soft processor core. The axi2JTAG core would be accessed over PCIE as a set of registers.

Has someone done this before?

Is it reasonable to write the configuration file needed? Examples of something similar, documentation?

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