I am using ST micro STR911FAW44X6 as SPI master to send out a hugh amount of data(136*256 bytes) to a SPI slave. I set up CLK as 10MHz, CPHA=0, CPOL=0.
The way I send out the data is as follows:
for ( j = 0; j < 100; j++)
SSP1->DR = i;
while( ( SSP1->SR & 0x0001) == 0x0000 ); // wait transmit FIFO to be empty
It is supposed to send out data from 0x00 to 0xFF for 100 rounds. At beginning the slave receives the correct data. Then at about round 20, the data SPI slave received seems to be missing the last bit. For instance, the received data is supposed to be 0xFC, 0xFD, 0xFE, 0xFF; but the actual data received is 0xFC, 0x7E, 0xFF, 0x7F. Seems that the receive shift register did not received the last bit when 0xFD is sent out. It received 0x7E(meaning only 7bits are shifted in). It shifted the most significant 7bits of 0xFD, then all subsequent bytes are messed up. Do you know how I can fix it from the MCU transmit side given that the slave code is fixed? I tried to put delay after while loop but did not work.