SparkFun Forums

[bigglez]

Greetings Trevor,

as for memory ill need ((130,000x24)x2) ~6.5Mb ram that has a maximum transfer rate of 111ns so it will never fall behind the scan.

I'm thinking through the memory requirements,
Here's my numbers.
The display is 480 x 272 pixels = 130,560
Each pixel is 24 bits = 130,560 x 24 = 3,133,440
Each memory plane is = 3,133,440/8 = 391,680 Bytes
Ping Pong buffer has two planes = 391,680 * 2 = 783,360 Bytes

You only need one meg Byte of RAM to support
this display. A SRAM would be much easier to use
(than a DRAM).

For your prototype don't bother compressing the
display into contiguous addresses, just "waste"
the end of each row and a few more rows at the
bottom of the display to simplify the addressing.
Round up the memory to a stock size.

The new memory map is now 512 x 512 x 24b,
the H address and the V address are both 9 bits.
512 x 512 x 3 x 2 = 1,572,864 Bytes

Perhaps it makes more sense to get three physical
memory chips, one each for the RGB data?

As there are many 16b memory maps, perhaps
the memory outputs 16b and a latch saves 8b
for the next PIXEL, thus cutting the memory
speed in half. Or, read 16b from the memory
and use the next memory cycle for a write?

The dual port memory seems much more expensive
than Async SRAM.

Should be interesting to see what you end up with.

On other thought, to light up the display you don't
need any memory. Once you have the H and V
syncs applied you can toggle the high order bits of
the PIXEL data and get colour blocks on the screen.
(Not much different from the "colour organ" you had
in your OP).

Comments Welcome!

[iceblu3710]

I was searching around and the majority of dual-port sram is <128kB*16b and I would need 1MB*24b or three 512kb*8b which would be cheeper anyways. Using sram I would think it would need to be at least twice as fast as its dual-port counterpart because only one device can address/read at a time.

Im going to focus on clock generation and just get the thing lit as its a good motivator to see something actually work. Ive not done any fpga/clpd work before and the Verilog language looks very strange... any tutorials/dev boards you could recommend for a SPG? I was thinking of just using one of my pics as it should be capable of generating a signal close enough for the time being.

The product page shows the psp screen hooked up to the spartan fpga which is pretty expensive, however the http://www.sparkfun.com/commerce/produc ... ts_id=8110 is quite cheep. As i do not see any ram on the spartan-screen setup I imagine their using the spartan as the ram as theirs like >300k logic blocks to play with.

[bigglez]

Greetings Trevor,

I was searching around and the majority of dual-port sram is <128kB*16b and I would need 1MB*24b or three 512kb*8b which would be cheeper anyways. Using sram I would think it would need to be at least twice as fast as its dual-port counterpart because only one device can address/read at a time.

I'd be interested in your pricing for SRAM.

The display is not logical (binary powers for H and V) so
a binary sized memory has unused space (as noted earlier).
The write to memory can be done during the retrace
periods (i.e. after the H line has dumped to the LCD,
the rest of the time period before the next line is
available for writing. Plus we have full H time for several
V periods at the bottom of the LCB active area. Of course,
with ping-pong memory you write to the hidden plane
for one entire scan of the LCD plus the dead time at
each retrace period.

This approach encouraged me to give up on
dual-port SRAM to start. Once the LCD lights up the
next step would be to drive single port SRAM for
reading to the LCD and writing from the uC.

Remeber, 50ns memory would get two read (or one
read and one write) in 111ns (the LCD clock).

Im going to focus on clock generation and just get the thing lit as its a good motivator to see something actually work. Ive not done any fpga/clpd work before and the Verilog language looks very strange... any tutorials/dev boards you could recommend for a SPG? I was thinking of just using one of my pics as it should be capable of generating a signal close enough for the time being.

I don't have any experience with FPGAs, so I'd start with
combinational logic using synchronous counters (as I've
done several TV related projects that way).

Basically a clock is used by the LCD (at 9MHz) and a
counter is divided down to H rate, and reset at the
end of the active line. Pick off from the counter chain
give us binary addresses for the H position and also
H sync (with correct timing relative to column 1).

The H sync advances a second counter chain for the
vertical. We now have access to all H and V binary
addresses for the LCD. These map directly to the
memory (when that part is constructed).

For the 'first look testing' any of the H or
V address lines can feed the LCD RGB inputs to make
lines. A little more work with the addresses and some
gates and you can display blocks or rectangles on the
LCD.

A uC would probably give the right H and V pulses,
but it won't give the fully binary address. We'd need
eighteen IOs (nine each for H and V addresses).

Yes this is a lot of logic to wire up on a proto board,
almost worth making a PCB and using SMT parts...

Comments Welcome!

[iceblu3710]

T_T I overthought my clocks again, im so ueto having a bunch of picks at my fingertips to spit out what I need I forgot theirs perfectly good combi-logic to get the job done and be more precise about it.

Having the H & V in 9bit binary would be a major advantage of not needing a uC to organize the next line for output as you could directly pipe it into the ram's address bus. Also would give me a good feedback loop for the uC to know exactly what pixle is being drawn so I don't overwrite data yet to be displayed. (though i could do all this with basic logic and just have an interrupt saying when its safe to write the next frame in ram)

My prices suck, I don't have a student discount anymore at my local dealer as I just moved to Vancouver, BC, Canada last month. So I use Mouser and Digi-key again. In case your wondering im a 4th year electrician, I work 7months goto trade school for 8weeks and one semester at university for electronics engineering. One more year and hopefully sept 2009 ill be full time in uni for my last 3years of engineering.

Where do you get your ram from? any you recommend in particular, I have found a few 512k sram thats 12-15ns but their all 'call for prices' or minimum 1k orders.

[Philba]

jameco carries a fair number of SRAMs. Some of the prices aren't bad but their dual port stuff is way pricey.

[iceblu3710]

Found this on Jameco http://www.jameco.com/Jameco/Products/ProdDS/157358.pdf

512x512x8bit = 2098kbit/frame *2 = 4.2Mbit ram/color channel
10x9 H/V decode just like I need, 55-70us is iffy but the $19.19 each is rape!

Screens only cost $68, I sure don't wanna spend another $60 just to make em dance, especially when I have several of them.

Ill keep looking for ram and some synchronous counters examples, Ive got one worked out in my head but would like to compare before I order more parts. I wonder if National Instruments Circuit Design Suite or Altium Designer would let me simulate without having to learn another bloody language...

[Philba]

I'd think about it a bit differently. How about 2 of these:
http://www.jameco.com/webapp/wcs/stores ... tId=392358
or four for double buffered. It's wicked fast. 16X wide would be pretty easy to use and 2 in parallel would feed the display in a single cycle. Yeah, you waste a byte per pixel but it's less than $20 for all the RAM.

By the way, you might want to rethink the double buffering idea depending on your application. If you will only be updating parts of the display, double buffering is going to be a bit of a pain. If you will continually refresh the display (like for video), it will be fine. There are lots of techniques for dealing with a single frame buffer so you don't get tearing and such.

[iceblu3710]

Awesome, thanks for the link Philba, not only is it wickid fast and stupidly easy to interface you cant beat $5. Im going to try for a non ping-pong setup first as ive got a few ideas how to get anyway with things.

TSOPII T_T ill definitely be making a breakout board for that guy, im in the process of getting down to Seattle, well Everett actually to buy a mini mill as the last few trips to batchPCB I've gotten wonderful boards that I designed as coasters... less waiting to discover a mistake when you can mill yourself.

Now to design my clock generator, should keep me occupied during the week while I'm waiting for shipments

[Philba]

you know there's a grizzley store in B'ham? check out their online catalogs. pretty good prices.

[bigglez]

Greetings Trevor,
Did you buy your PSP LCD from SFE? I see they're
out of stock, but there are many to be had on eBay.

The FPC (Flex Printed Circut) requires a fine-pitch
mating connector (SFE has these), and SFE shows
a breakout/interface PCB but I can see that board
listed on their site. Is it a real product?

Comments Welcome!

[iceblu3710]

SFE shows
a breakout/interface PCB but I can see that board
listed on their site. Is it a real product?

My friend overseas got 6screens off a chinese site and we both used one to replace our dead ones in our psp's. I paied ~$18/screen so it was a wickid deal.

In the psp 3rd picture they have their own breakout board for that spartan fpga but it looks to be just the proof on concept as theirs a few random wires. I should ask if their thinking of making a breakout. Would be helpful to have all the voltage reg/clock already delt with...

Bellingham is much closer to me, I could almost get their after work, thanks

[iceblu3710]

Random update, VHDL isn't so hard.. kinda.. writing if like c statements is defiantly easier to visualize than doing it on schematics.

http://search.digikey.com/scripts/DkSea ... 06-1048-ND

512x512x16 for $11, would need two but the next cheapest all in one is over $30, just toggle the OE bit and should work just fine, maybe make use of the extra space for drawing functions or something.

I could also cut down to 4 or 6bit color input, easier to get a 4.5M(512k*18).
http://search.digikey.com/scripts/DkSea ... 50AJXCT-ND

Also a though, Xilinx has distributed ram using logic blocks as ram, It might even be cheaper to run all the signal generation and build the entire ram into the fpga. Provided I could get 3M (480x272x42) onto a 500k spartan-3 chip, not that fan into fooling around yet.

[pma]

Digilent has a $99 board that might suite your needs:
http://www.digilentinc.com/Products/Cat ... le%20Logic
You would need to deal with that Hirose connector; Digilent makes a breakout board for that.

Once upon a time, I prototyped something with an 8-bit 480x320 STN display, clocking at 13MHz. It was based on a Nexys board, with a XC3S1000, and Micron PSRAM attached to it. PSRAM presents you with a SRAM-like interface -- all you need to do is make sure you release the chip select periodically, so that self-refresh can occur. I ran the PSRAM at 66MHz. A state machine arbitrated between CPU writes and reads for the LCD. This is when FIFOs in FPGAs are very helpful.

I also used IP-core processors inside the FPGA.
Experimented with picoblaze (http://www.xilinx.com/products/ipcenter ... V2-Pro.htm), but could not deal with the 256-byte code-size restrictions.
Then I looked at Microchip PIC implementation (http://www.opencores.org/projects.cgi/w ... 4/overview). Had a better time with that. Even tried to update the core to support PIC MPLAB ICD2 emulation, but did not get too far before I had to move onto other things.

EDIT:
If you are interested, you can look at my Xilinx project files (not quite sure what state they are in and no documentation, but here you go!):
http://www.mediamatech.com/files/scope_fpga.zip (PIC CPU)
http://www.mediamatech.com/files/scope_fpga_PB.zip (PicoBlaze CPU)
Note that everything is written in Verilog.

Regards,
Pete[/url]